Datasheet Cypress CY8C24223A-12PVXET — 数据表

CY8C24123A CY8C24223A CY8C24423A PSoC® Programmable System-on-Chip
PSoC® Programmable System-on-Chip Features Powerful Harvard-architecture processor M8C processor speeds up to 24 MHz 8 Ч 8 multiply, 32-bit accumulate Low power at high speed Operating voltage: 2.4 V to 5.25 V Operating voltages down to 1.0 V using on-chip switch mode pump (SMP) Industrial temperature range: ­40 °C to +85 °C Advanced peripherals (PSoC® blocks) Six rail-to-rail analog PSoC blocks provide: Up to 14-bit analog-to-digital converters (ADCs) Up to 9-bit digital-to-analog converters (DACs) Programmable gain amplifiers (PGAs) Programmable filters and comparators Four digital PSoC blocks provide: 8- to 32-bit timers and counters, 8- and 16-bit pulse-width modulators (PWMs) Cyclical redundancy check (CRC) and pseudo random sequence (PRS) modules Full-duplex universal asynchronous receiver transmitter (UART) Multiple serial peripheral interface (SPI) masters or slaves Can connect to all general-purpose I/O (GPIO) pins Complex peripherals by combining blocks Precision, programmable clocking Internal ±5% 24- / 48-MHz main oscillator High accuracy 24 MHz with optional 32 kHz crystal and phase-locked loop (PLL) Optional external oscillator up to 24 MHz Internal oscillator for watchdog and sleep Flexible on-chip memory 4 KB flash program storage 50,000 erase/write cycles 256-bytes SRAM data storage In-system serial programming (ISSP) Partial flash updates Flexible protection modes Electronically erasable programmable read only memory (EEPROM) emulation in flash Programmable pin configurations 25-mA sink, 10-mA source on all GPIOs Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs Eight standard analog inputs on all GPIOs, and four additional analog inputs with restricted routing Two 30 mA analog outputs on all GPIOs Configurable interrupt on all GPIOs New CY8C24x23A PSoC device Derived from the CY8C24x23 device Low power and low voltage (2.4 V) Additional system resources 2 I C slave, master, and multi-master to 400 kHz Watchdog and sleep timers User-configurable low-voltage detection (LVD) Integrated supervisory circuit On-chip precision voltage reference Complete development tools Free development software (PSoC DesignerTM) Full-featured, in-circuit emulator (ICE), and programmer Full-speed emulation Complex breakpoint structure 128 KB trace memory Logic Block Diagram
Port 2 Port 1 Port 0 Analog Drivers PSoC CORE
System Bus
Global Digital Interconnect SRAM 256 Bytes Interrupt Controller SROM Global Analog Interconnect Flash 4KB Sleep and Watchdog CPU Core (M8C) …