Datasheet Cypress CY8C4245AXI-483 — 数据表

Programmable System-on-Chip (PSoC )
General Description PSoC® 4: PSoC 4200 Family Datasheet ® PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system controllers with an ARM® CortexTM-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a microcontroller with digital programmable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design. Features
32-bit MCU Sub-system Serial Communication 48-MHz ARM Cortex-M0 CPU with single cycle multiply Up to 32 kB of flash with Read Accelerator Up to 4 kB of SRAM Two independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality Programmable Analog Timing and Pulse-Width Modulation Two opamps with reconfigurable high-drive external and high-bandwidth internal drive, Comparator modes, and ADC input buffering capability 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin Two low-power comparators that operate in Deep Sleep mode Four 16-bit timer/counter pulse-width modulator (TCPWM) blocks Center-aligned, Edge, and Pseudo-random modes Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Up to 36 Programmable GPIOs Any GPIO pin can be CapSense, LCD, analog, or digital Drive modes, strengths, and slew rates are programmable Programmable Digital Four programmable logic blocks called universal digital blocks, (UDBs), each with 8 Macrocells and data path Cypress-provided peripheral component library, user-defined state machines, and Verilog input Five different packages 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 35-ball WLCSP, and 28-pin SSOP package 35-ball WLCSP package is shipped with I2C Bootloader in Flash Low Power 1.71-V to 5.5-V Operation 20-nA Stop Mode with GPIO pin wakeup Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs PSoC Creator Design Environment Capacitive Sensing Integrated Development Environment (IDE) provides schematic design entry …