Datasheet Texas Instruments TLV1571CDW — 数据表
| 制造商 | Texas Instruments |
| 系列 | TLV1571 |
| 零件号 | TLV1571CDW |
1通道10位1.25 MSPS ADC 8通道，DSP / SPI，硬件可配置，低功耗24-SOIC 0至70
数据表
2.7 V to 5.5 V, 1-/-8 Channel 10-Bit Parallel Analog-to-Digital Converters datasheet
PDF, 627 Kb, 修订版: D, 档案已发布: Jul 11, 2000
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价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 24 |
| Package Type | DW |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | TLV1571C |
| Width (mm) | 7.5 |
| Length (mm) | 15.4 |
| Thickness (mm) | 2.35 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.65 |
| Mechanical Data | 下载 |
参数化
| # Input Channels | 1 |
| Analog Voltage AVDD(Max) | 5.5 V |
| Analog Voltage AVDD(Min) | 2.7 V |
| Architecture | SAR |
| Digital Supply(Max) | 5.5 V |
| Digital Supply(Min) | 2.7 V |
| INL(Max) | 1 +/-LSB |
| Input Range(Max) | 5.5 V |
| Input Type | Single-Ended |
| Integrated Features | Oscillator |
| Interface | Parallel |
| Multi-Channel Configuration | N/A |
| Operating Temperature Range | -40 to 85,0 to 70 C |
| Package Group | SOIC |
| Package Size: mm2:W x L | 24SOIC: 160 mm2: 10.3 x 15.5(SOIC) PKG |
| Power Consumption(Typ) | 12 mW |
| Rating | Catalog |
| Reference Mode | Ext |
| Resolution | 10 Bits |
| SINAD | 60 dB |
| SNR | 60 dB |
| Sample Rate (max) | 1.25MSPS SPS |
| Sample Rate(Max) | 1.25 MSPS |
| THD(Typ) | -60 dB |
生态计划
| RoHS | Compliant |
应用须知
- Interfacing the TLV1571/78 Analog-to-Digital Converter to the TMS320C542 DSPPDF, 192 Kb, 档案已发布: Oct 7, 1999
This application report presents a hardware solution for interfacing the TLV1571/TLV1578 10-bit, 1.25 MSPS low-power analog-to-digital converter (ADC) to the 16-bit fixed-point TMS320C542 digital signal processor (DSP). The report describes the interface hardware and C-callable software routines, which support communication between ADC and DSP. - Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, 档案已发布: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
模型线
系列: TLV1571 (4)
- TLV1571CDW TLV1571IDW TLV1571IDWG4 TLV1571IPW
制造商分类
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)