Datasheet Texas Instruments CD74HC4046ANSR — 数据表

制造商	Texas Instruments
系列	CD74HC4046A
零件号	CD74HC4046ANSR

带有VCO 16-SO的高速CMOS逻辑锁相环-55至125

数据表

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PDF, 833 Kb, 修订版: J, 档案已发布: Nov 21, 2003

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价格

状态

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

打包

Pin	16
Package Type	NS
Industry STD Term	SOP
JEDEC Code	R-PDSO-G
Package QTY	2000
Carrier	LARGE T&R
Device Marking	HC4046AM
Width (mm)	5.3
Length (mm)	10.3
Thickness (mm)	1.95
Pitch (mm)	1.27
Max Height (mm)	2
Mechanical Data	下载

参数化

Bits	1
F @ Nom Voltage(Max)	70 Mhz
ICC @ Nom Voltage(Max)	0.08 mA
Operating Temperature Range	-55 to 125 C
Output Drive (IOL/IOH)(Max)	5.2/-5.2 mA
Package Group	SO
Package Size: mm2:W x L	16SO: 80 mm2: 7.8 x 10.2(SO) PKG
Rating	Catalog
Technology Family	HC
VCC(Max)	6 V
VCC(Min)	2 V
Voltage(Nom)	3.3,5 V
tpd @ Nom Voltage(Max)	64 ns

生态计划

RoHS

Compliant

应用须知

下载
Implementation of FSK Modulation and Demodulation using CD74HC4046A
PDF, 1.3 Mb, 档案已发布: Nov 25, 2013
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CMOS Phase-Locked-Loop Applications (Rev. B)
PDF, 687 Kb, 修订版: B, 档案已发布: Sep 19, 2002
Applications of the HC/HCT4046A phase-locked loop (PLL) and HC/HCT7046A PLL with lock detection are provided including design examples with calculated and measured results. Features of these devices relative to phase comparators lock indicators voltage-controlled oscillators (VCOs) and filter design are presented.
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Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency
PDF, 860 Kb, 档案已发布: Mar 31, 2008
Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica
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Selecting the Right Texas Instruments Signal Switch
PDF, 769 Kb, 档案已发布: Sep 7, 2001
Texas Instruments offers a wide variety of electronic switches (digital analog bilateral bilateral analog) in a variety of families including CBT CBTLV HC LV and LVC. Depending on the application the right solution may be an analog switch that passes digital signals or vice versa. This application report summarizes the various switching technologies and provides considerations for choosi
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SN54/74HCT CMOS Logic Family Applications and Restrictions
PDF, 102 Kb, 档案已发布: May 1, 1996
The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal

模型线

系列: CD74HC4046A (15)

CD74HC4046AE CD74HC4046AEE4 CD74HC4046AM CD74HC4046AM96 CD74HC4046AM96E4 CD74HC4046AM96G4 CD74HC4046AMG4 CD74HC4046AMT CD74HC4046AMTE4 CD74HC4046ANSR CD74HC4046ANSRE4 CD74HC4046APWR CD74HC4046APWRE4 CD74HC4046APWRG4 CD74HC4046APWT

制造商分类

Semiconductors > Logic > Specialty Logic > Phase-Locked-Loop (PLL)/Oscillator