Datasheet Texas Instruments ADS8332IPWR — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADS8332 |
| 零件号 | ADS8332IPWR |
2.7V至5.5V，16位，500KSPS低功耗串行ADC，具有8通道MUX和Breakout 24-TSSOP -40至85
数据表
ADS833x Low-Power, 16-Bit, 500-kSPS, 4- and 8-Channel Unipolar Input Analog-to-Digital Converters With Serial Interface datasheet
PDF, 1.8 Mb, 修订版: E, 档案已发布: Aug 9, 2016
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 24 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | ADS8332 |
| Width (mm) | 4.4 |
| Length (mm) | 7.8 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| # Input Channels | 8 |
| Analog Voltage AVDD(Max) | 5.5 V |
| Analog Voltage AVDD(Min) | 2.7 V |
| Architecture | SAR |
| Digital Supply(Max) | 5.5 V |
| Digital Supply(Min) | 1.65 V |
| INL(Max) | 2 +/-LSB |
| Input Range(Max) | 4.2 V |
| Input Type | Pseudo-Differential,Single-Ended |
| Integrated Features | Daisy-Chainable |
| Interface | SPI |
| Multi-Channel Configuration | Multiplexed |
| Operating Temperature Range | -40 to 85 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) PKG |
| Power Consumption(Typ) | 14.2 mW |
| Rating | Catalog |
| Reference Mode | Ext |
| Resolution | 16 Bits |
| SINAD | 91 dB |
| SNR | 91.5 dB |
| Sample Rate (max) | 500kSPS SPS |
| Sample Rate(Max) | 0.5 MSPS |
| THD(Typ) | -101 dB |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- Evaluation Modules & Boards: ADS8332EVMV2-PDK
ADS8332 16-Bit 500KSPS Low-Power Serial ADC Evaluation Module Performance Demonstration Kit (PDK)
Lifecycle Status: Active (Recommended for new designs)
应用须知
- Interfacing the ADS8332 to the TMS320F28335 DSPPDF, 145 Kb, 档案已发布: Aug 20, 2012
ADS8332, ADS8331 Interfacing the ADS8332 to TMS320F28335 DSP LEAVE IN MS WORD - Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, 档案已发布: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
模型线
系列: ADS8332 (8)
制造商分类
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)