Datasheet Texas Instruments ADS5485IRGC25 — 数据表

制造商	Texas Instruments
系列	ADS5485
零件号	ADS5485IRGC25

数据表

价格

状态

打包

替代品

生态计划

设计套件和评估模块

• Evaluation Modules & Boards: THS770006EVM
  THS770006 Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
• Evaluation Modules & Boards: TSW1400EVM
  High Speed Data Capture and Pattern Generation Platform
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: TSW2200EVM
  TSW2200EVM: Low Cost Portable Power Supply
  Lifecycle Status: Active (Recommended for new designs)
  
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应用须知

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  Input Impedance Measurement Using ADC FFT Data
  PDF, 275 Kb, 档案已发布: Jan 11, 2011
  Texas Instruments has introduced a family of high-speed analog-to-digital converters (ADCs) suited tomeet the demand for high-speed and high-IF sampling systems. To achieve the highest overall system performance, an analog front-end circuit with an antialiasing filter must drive the ADC with the highestpossible dynamic range and lowest distortions. One important parameter of the front-end circ
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  High-Speed Analog-to-Digital Converter Basics
  PDF, 1.1 Mb, 档案已发布: Jan 11, 2012
  The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil
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  QFN Layout Guidelines
  PDF, 1.3 Mb, 档案已发布: Jul 28, 2006
  Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
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  Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  PDF, 2.0 Mb, 修订版: A, 档案已发布: May 22, 2015
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  Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  PDF, 1.2 Mb, 修订版: A, 档案已发布: Jul 19, 2013
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  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, 档案已发布: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
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  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
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  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, 档案已发布: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
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  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
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  Interleaving Analog-to-Digital Converters
  PDF, 64 Kb, 档案已发布: Oct 2, 2000
  It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error.
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  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
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  What Designers Should Know About Data Converter Drift
  PDF, 95 Kb, 档案已发布: Oct 2, 2000
  Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify.

模型线

制造商分类

• Semiconductors > Data Converters > Analog to Digital Converter > High Speed ADC (>10MSPS)