Datasheet Texas Instruments SN74ALVTH16374VR — 数据表

制造商	Texas Instruments
系列	SN74ALVTH16374
零件号	SN74ALVTH16374VR

具有三态输出的2.5V / 3.3V 16位边缘触发D类触发器48-TVSOP -40至85

数据表

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PDF, 928 Kb, 修订版: G, 档案已发布: Nov 9, 2006

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价格

状态

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

打包

Pin	48
Package Type	DGV
Industry STD Term	TVSOP
JEDEC Code	R-PDSO-G
Package QTY	2000
Carrier	LARGE T&R
Device Marking	VT374
Width (mm)	4.4
Length (mm)	9.7
Thickness (mm)	1.05
Pitch (mm)	.4
Max Height (mm)	1.2
Mechanical Data	下载

参数化

3-State Output	Yes
Bits	16
F @ Nom Voltage(Max)	250 Mhz
ICC @ Nom Voltage(Max)	5 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	64/-32 mA
Package Group	TVSOP
Package Size: mm2:W x L	48TVSOP: 62 mm2: 6.4 x 9.7(TVSOP) PKG
Rating	Catalog
Schmitt Trigger	No
Technology Family	ALVT
VCC(Max)	3.6 V
VCC(Min)	2.3 V
Voltage(Nom)	2.5,3.3 V
tpd @ Nom Voltage(Max)	3.8,3.2 ns

生态计划

RoHS

Compliant

应用须知

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Advanced Low-Voltage Technology
PDF, 59 Kb, 档案已发布: Jul 27, 1999
ALVT, the advanced low-voltage logic family, offers high-performance BiCMOS devices that are functional at 3.3-V and 2.5-V V sub CC and have low propagation delay, low static-power consumption, and 64 mA current drive. Other features include 5-V tolerance; auto3-state; bus hold; partial power down, hot insertion, and live insertion; and excellent simultaneous-switching and output-skew performance.
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Bus-Hold Circuit
PDF, 418 Kb, 档案已发布: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
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16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
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Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
PDF, 154 Kb, 修订版: A, 档案已发布: Sep 8, 1999
In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families
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Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
PDF, 209 Kb, 档案已发布: May 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

模型线

系列: SN74ALVTH16374 (6)

74ALVTH16374ZQLR SN74ALVTH16374DL SN74ALVTH16374DLR SN74ALVTH16374GR SN74ALVTH16374KR SN74ALVTH16374VR

制造商分类

Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop