Datasheet Texas Instruments CD74AC323M — 数据表
制造商 | Texas Instruments |
系列 | CD74AC323 |
零件号 | CD74AC323M |
具有通用并行I / O引脚和同步复位的8输入通用移位/存储寄存器20-SOIC -55至125
数据表
8-Input Universal Shift/Storage Register with Common Parallel I/O Pins datasheet
PDF, 1.2 Mb, 档案已发布: Dec 3, 1998
从文件中提取
价格
状态
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
打包
Pin | 20 |
Package Type | DW |
Industry STD Term | SOIC |
JEDEC Code | R-PDSO-G |
Package QTY | 25 |
Carrier | TUBE |
Device Marking | AC323M |
Width (mm) | 7.5 |
Length (mm) | 12.8 |
Thickness (mm) | 2.35 |
Pitch (mm) | 1.27 |
Max Height (mm) | 2.65 |
Mechanical Data | 下载 |
参数化
3-State Output | Yes |
F @ Nom Voltage(Max) | 100 Mhz |
ICC @ Nom Voltage(Max) | 0.16 mA |
Operating Temperature Range | -55 to 125 C |
Output Drive (IOL/IOH)(Max) | 24/-24 mA |
Package Group | SOIC |
Package Size: mm2:W x L | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) PKG |
Rating | Catalog |
Schmitt Trigger | No |
Technology Family | AC |
VCC(Max) | 5.5 V |
VCC(Min) | 1.5 V |
Voltage(Nom) | 1.5,3.3,5 V |
tpd @ Nom Voltage(Max) | 147,16.5,11.7 ns |
生态计划
RoHS | Compliant |
应用须知
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, 修订版: A, 档案已发布: Feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, 档案已发布: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
模型线
系列: CD74AC323 (1)
- CD74AC323M
制造商分类
- Semiconductors > Logic > Flip-Flop/Latch/Register > Shift Register