Datasheet Texas Instruments ADS62P49IRGCT — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADS62P49 |
| 零件号 | ADS62P49IRGCT |
双通道14位250MSPS模数转换器（ADC）64-VQFN -40至85
数据表
Dual Channel 14-/12-Bit, 250/210 MSPS ADC with DDR LVDS & Parallel CMOS Outputs datasheet
PDF, 2.4 Mb, 修订版: B, 档案已发布: Jan 4, 2011
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 64 |
| Package Type | RGC |
| Industry STD Term | VQFN |
| JEDEC Code | S-PQFP-N |
| Package QTY | 250 |
| Carrier | SMALL T&R |
| Device Marking | AZ62P49 |
| Width (mm) | 9 |
| Length (mm) | 9 |
| Thickness (mm) | .88 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1 |
| Mechanical Data | 下载 |
参数化
| # Input Channels | 2 |
| Analog Input BW | 700 MHz |
| Architecture | Pipeline |
| DNL(Max) | 1.3 +/-LSB |
| DNL(Typ) | 0.6 +/-LSB |
| ENOB | 11.3 Bits |
| INL(Max) | 5 +/-LSB |
| INL(Typ) | 2.5 +/-LSB |
| Input Buffer | No |
| Input Range | 2 Vp-p |
| Interface | DDR LVDS,Parallel CMOS |
| Operating Temperature Range | -40 to 85 C |
| Package Group | VQFN |
| Package Size: mm2:W x L | 64VQFN: 81 mm2: 9 x 9(VQFN) PKG |
| Power Consumption(Typ) | 1250 mW |
| Rating | Catalog |
| Reference Mode | Ext,Int |
| Resolution | 14 Bits |
| SFDR | 85 dB |
| SINAD | 72.7 dB |
| SNR | 73 dB |
| Sample Rate(Max) | 250 MSPS |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- Evaluation Modules & Boards: TSW2170EVM
TSW2170 Crystal Filtered 70MHz Source Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: TSW1405EVM
Data Capture: Data Converter EVMs With 8 LVDS Lanes up to 1.0Gbps
Lifecycle Status: Active (Recommended for new designs)
应用须知
- QFN Layout GuidelinesPDF, 1.3 Mb, 档案已发布: Jul 28, 2006
Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs. - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, 档案已发布: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, 档案已发布: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, 档案已发布: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
模型线
系列: ADS62P49 (2)
- ADS62P49IRGCR ADS62P49IRGCT
制造商分类
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)