PDF, 152 Kb, 修订版: A, 档案已发布: Jun 16, 2008
This application report describes how to use the existing enhanced direct memory access (EDMA3) driver on the TMS320DM643x device. It explains several complicated transfers required for certain real-life application using the EDMA3.
PDF, 268 Kb, 修订版: E, 档案已发布: Mar 23, 2012
This document describes the functionality of the DM643x ROM bootloader software. Please note that the ROM bootloader requires use of Application Image Script (AIS) as the primary data format for loading code/data. AIS is a Texas Instruments, Inc. proprietary data format. AIS is explained in detail in Section 3 of this document.
PDF, 225 Kb, 修订版: A, 档案已发布: Nov 14, 2007
This application report describes how to use the existing video processing back end (VPBE) and video processing front end (VPFE) driver on the TMS320DM643x devices. The VPBE block is comprised of the on-screen display (OSD) and the video encoder (VENC) modules. The VPFE is comprised of five modules: charge-coupled device (CCD) controller (CCDC), resizer, preview, hardware 3A statistic generator (H
PDF, 135 Kb, 修订版: C, 档案已发布: May 10, 2010
Note: PRELIMINARY DATA FOR TMX DEVICES. INFORMATION SUBJECT TO CHANGEThis application report discusses power consumption of the Texas Instruments TMS320DM643x Digital Media Processor (DMP). Power consumption is highly application-dependent, so a spreadsheet is provided to model power consumption for your applications.Note: TMX devices are experimental devices that are not necessa
PDF, 1.8 Mb, 档案已发布: Jul 6, 2007
The DM643x devices use a great deal of internal pin multiplexing to allow the most functionality in the smallest and lowest cost package. The software accompanying this application report allows the pin multiplexing registers of the device to be calculated with ease, as well as showing what peripherals can be used together and what devices of the DM643x family support the peripherals that are sele
PDF, 150 Kb, 修订版: A, 档案已发布: Jun 26, 2008
This application report contains implementation instructions for the DDR2 interface contained on the TMS320DM643x digital signal processor (DSP) device. The approach to specifying interface timing for the DDR2 interface is quite different than on previous devices.The previous approach specified device timing in terms of data sheet specifications and simulation models. The system designer was
PDF, 302 Kb, 档案已发布: Oct 9, 2008
PDF, 108 Kb, 修订版: A, 档案已发布: Jan 4, 2007
PDF, 469 Kb, 修订版: B, 档案已发布: Jul 17, 2008
The image-scaling operation is one of the most commonly used video and imaging processing functions. The resizer hardware module in the DaVinciв„ў video processing subsystem (VPSS) provides the scaling capability in hardware, therefore off-loading the system for other processing tasks. To achieve good video quality while maintaining good overall system performance, a better understanding of th
PDF, 209 Kb, 修订版: A, 档案已发布: Jul 23, 2008
The Preview Engine block in the DaVinci video processing sub-system (VPSS) provides some critical functions for image and video processing. These functions, if implemented in software, require a significant number of computations in terms of million instructions per second (MIPs). By offloading these functions, the valuable MIPs can be used for more differentiating tasks, such as video compression
PDF, 741 Kb, 档案已发布: Oct 9, 2008
PDF, 310 Kb, 档案已发布: Oct 9, 2008
PDF, 550 Kb, 档案已发布: Oct 9, 2008
PDF, 292 Kb, 修订版: A, 档案已发布: Aug 21, 2008
This application report summarizes the key differences between the enhanced direct memory access (EDMA3) used on C64x+в„ў DSP devices and the EDMA2 used on TMS320C64xв„ў DSP devices, and provides guidance for migrating from EDMA2 to EDMA3.
PDF, 310 Kb, 修订版: A, 档案已发布: Oct 20, 2005
This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP
PDF, 1.6 Mb, 修订版: B, 档案已发布: Aug 13, 2015
PDF, 93 Kb, 修订版: A, 档案已发布: Jul 17, 2008
This application report motivates the way the DDR high-speed timing requirements are now going to be communicated to system designers. The traditional method of using data sheet parameters and simulation models is tedious. The system designer uses this information to evaluate whether timing specifications are met and can be expected to operate reliably.Ultimately, the real question the hardwa
PDF, 125 Kb, 档案已发布: Apr 15, 2009
PDF, 535 Kb, 档案已发布: Oct 6, 2011
The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then
