Datasheet Texas Instruments CD54HCT4046AF3A — 数据表

制造商	Texas Instruments
系列	CD54HCT4046A
零件号	CD54HCT4046AF3A

数据表

价格

状态

打包

参数化

生态计划

应用须知

• 下载
  Implementation of FSK Modulation and Demodulation using CD74HC4046A
  PDF, 1.3 Mb, 档案已发布: Nov 25, 2013
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  CMOS Phase-Locked-Loop Applications (Rev. B)
  PDF, 687 Kb, 修订版: B, 档案已发布: Sep 19, 2002
  Applications of the HC/HCT4046A phase-locked loop (PLL) and HC/HCT7046A PLL with lock detection are provided including design examples with calculated and measured results. Features of these devices relative to phase comparators lock indicators voltage-controlled oscillators (VCOs) and filter design are presented.
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  SN54/74HCT CMOS Logic Family Applications and Restrictions
  PDF, 102 Kb, 档案已发布: May 1, 1996
  The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal
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  TI IBIS File Creation Validation and Distribution Processes
  PDF, 380 Kb, 档案已发布: Aug 29, 2002
  The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
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  Implications of Slow or Floating CMOS Inputs (Rev. D)
  PDF, 260 Kb, 修订版: D, 档案已发布: Jun 23, 2016
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  Designing With Logic (Rev. C)
  PDF, 186 Kb, 修订版: C, 档案已发布: Jun 1, 1997
  Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
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  CMOS Power Consumption and CPD Calculation (Rev. B)
  PDF, 89 Kb, 修订版: B, 档案已发布: Jun 1, 1997
  Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
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  Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
  PDF, 614 Kb, 修订版: C, 档案已发布: Dec 2, 2015
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  Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
  PDF, 337 Kb, 档案已发布: Jul 8, 2004
  Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
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  Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
  PDF, 43 Kb, 档案已发布: Apr 1, 1996
  Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
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  Introduction to Logic
  PDF, 93 Kb, 档案已发布: Apr 30, 2015

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• Semiconductors > Space & High Reliability > Logic Products > Specialty Logic Products > Phase-Locked-Loop (PLL)Products/Oscillators