Datasheet Texas Instruments ADS41B29IRGZT — 数据表

制造商	Texas Instruments
系列	ADS41B29
零件号	ADS41B29IRGZT

数据表

价格

状态

打包

参数化

生态计划

设计套件和评估模块

• Evaluation Modules & Boards: ADS41B29EVM
  ADS41B29 12-Bit, 250-MSPS Analog-to-Digital Converter Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: ADS4149EVM
  ADS4149 14-Bit, 250-MSPS Analog-to-Digital Converter Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: TSW3085EVM
  Wideband Transmit Signal Chain Evaluation Board and Reference Design
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: TSW2200EVM
  TSW2200 Low-Cost Portable Power Supply Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: TSW1405EVM
  Data Capture: Data Converter EVMs With 8 LVDS Lanes up to 1.0Gbps
  Lifecycle Status: Active (Recommended for new designs)
  
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应用须知

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  Power Supply Design for the ADS41xx (Rev. A)
  PDF, 401 Kb, 修订版: A, 档案已发布: Dec 29, 2011
  System designers traditionally power the high-speed data converter in their systems from a low-noise, low-dropout linear regulator (LDO) in order to achieve the performance described in the analog-to-digital converter (ADC) data sheet. However, LDOs inherently are not very power efficient. Switching regulators, on the other hand, offer good power efficiency but typically come with higher output no
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  High-Speed Analog-to-Digital Converter Basics
  PDF, 1.1 Mb, 档案已发布: Jan 11, 2012
  The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil
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  Band-Pass Filter Design Techniques for High-Speed ADCs
  PDF, 733 Kb, 档案已发布: Feb 27, 2012
  Several well-known methods exist for designing passive inductor-capacitor (LC) filters with resistive load terminations. However, when LC filters are used to drive the analog input pins of a high-speed analog-to-digital converter (ADC), special consideration must be given to the ADC input impedance. Not accounting for the ADC input impedance often results in a filter design that does not meet the
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  QFN Layout Guidelines
  PDF, 1.3 Mb, 档案已发布: Jul 28, 2006
  Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
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  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, 档案已发布: Sep 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
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  Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  PDF, 1.2 Mb, 修订版: A, 档案已发布: Jul 19, 2013
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  Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  PDF, 2.0 Mb, 修订版: A, 档案已发布: May 22, 2015
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  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, 档案已发布: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
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  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
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  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015

模型线

制造商分类

• Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)