Datasheet Texas Instruments DM388AAAR21 — 数据表

DM385, DM388
www.ti.com SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 DM385 and DM388 DaVinci™ Digital Media Processor
Check for Samples: DM385, DM388 1 High-Performance System-on-Chip (SoC)
1.1 Features 1234 High-Performance DaVinci Digital Media
Processors
– Up to 1000-MHz ARM® Cortex™-A8 RISC
Processor
– Up to 2000 ARM Cortex-A8 MIPS ARM Cortex-A8 Core
– ARMv7 Architecture In-Order, Dual-Issue, Superscalar
Processor Core NEONв„ў Multimedia Architecture Supports Integer and Floating Point JazelleВ® RCT Execution Environment ARM Cortex-A8 Memory Architecture
– 32KB of Instruction and Data Caches
– 256KB of L2 Cache with ECC
– 64KB of RAM, 48KB of Boot ROM 256KB of On-Chip Memory Controller (OCMC)
RAM Imaging Subsystem (ISS)
– Camera Sensor Connection Parallel Connection for Raw (up to 16-Bit)
and BT.656/BT.1120 (8-or 16-Bit) CSI2 Serial Connection
– Image Sensor Interface (ISIF) for Handling
Image and Video Data From the Camera
Sensor
– Image Pipe Interface (IPIPEIF) for Image and
Video Data Connection Between Camera
Sensor, ISIF, IPIPE, and DRAM
– Image Pipe (IPIPE) for Real-Time Image and …