Datasheet Texas Instruments SN74AVC16646DGVR — 数据表

制造商	Texas Instruments
系列	SN74AVC16646
零件号	SN74AVC16646DGVR

具有三态输出的16位总线收发器和寄存器56-TVSOP -40至85

数据表

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PDF, 396 Kb, 修订版: F, 档案已发布: Apr 3, 2000

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价格

状态

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

打包

Pin	56
Package Type	DGV
Industry STD Term	TVSOP
JEDEC Code	R-PDSO-G
Package QTY	2000
Carrier	LARGE T&R
Device Marking	CVA646
Width (mm)	4.4
Length (mm)	11.3
Thickness (mm)	1.05
Pitch (mm)	.4
Max Height (mm)	1.2
Mechanical Data	下载

参数化

Bits	16
F @ Nom Voltage(Max)	200 Mhz
ICC @ Nom Voltage(Max)	0.04 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	-12/12 mA
Package Group	TVSOP
Package Size: mm2:W x L	56TVSOP: 72 mm2: 6.4 x 11.3(TVSOP) PKG
Rating	Catalog
Schmitt Trigger	No
Technology Family	AVC
VCC(Max)	3.6 V
VCC(Min)	1.2 V
Voltage(Nom)	1.2,1.5,1.8,2.5,3.3 V
tpd @ Nom Voltage(Max)	4.2,4.8,4.3,3.1,2.6 ns

生态计划

RoHS

Compliant

应用须知

下载
Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)
PDF, 126 Kb, 修订版: B, 档案已发布: Jul 7, 1999
Texas Instruments (TI[TM]) next-generation logic is called the Advanced Very-low-voltage CMOS (AVC) family. The AVCfamily features TI?s Dynamic Output Control (DOC[TM]) circuit (patent pending). DOC circuitry automatically lowers the outputimpedance of the circuit at the beginning of a signal transition, providing enough current to achieve high signaling speeds, thensubsequently raises the i
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AVC Logic Family Technology and Applications (Rev. A)
PDF, 148 Kb, 修订版: A, 档案已发布: Aug 26, 1998
Texas Instruments (TI?) announces the industry?s first logic family to achieve maximum propagation delays of less than 2 ns at 2.5 V. TI?s next-generation logic is the Advanced Very-low-voltage CMOS (AVC) family. Although optimized for 2.5-V systems, AVC logic supports mixed-voltage systems because it is compatible with 3.3-V and 1.8-V devices. The AVC family features TI?s Dynamic Output Control (
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Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)
PDF, 390 Kb, 修订版: B, 档案已发布: Apr 30, 2015
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16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa

模型线

系列: SN74AVC16646 (1)

SN74AVC16646DGVR

制造商分类

Semiconductors > Logic > Buffer/Driver/Transceiver > Registered Transceiver