[ /Title
(CD54H
C74,
CD74H
C74,
CD74H
CT74)
/Subject
(Dual D
FlipFlop
with Set CD54HC74, CD74HC74,
CD54HCT74, CD74HCT74
Data sheet acquired from Harris Semiconductor
SCHS124D Dual D Flip-Flop with Set and Reset
Positive-Edge Trigger January 1998 -Revised September 2003 Features Description Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times The ’HC74 and ’HCT74 utilize silicon gate CMOS technology
to achieve operating speeds equivalent to LSTTL parts.
They exhibit the low power consumption of standard CMOS
integrated circuits, together with the ability to drive 10 LSTTL
loads. Asynchronous Set and Reset Complementary Outputs This flip-flop has independent DATA, SET, RESET and
CLOCK inputs and Q and Q outputs. The logic level present
at the data input is transferred to the output during the
positive-going transition of the clock pulse. SET and RESET …
