Datasheet Texas Instruments ADS54RF63IPFPR — 数据表

制造商	Texas Instruments
系列	ADS54RF63
零件号	ADS54RF63IPFPR

数据表

价格

状态

打包

参数化

生态计划

设计套件和评估模块

• Evaluation Modules & Boards: TSW2170EVM
  TSW2170 Crystal Filtered 70MHz Source Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: TSW2200EVM
  TSW2200 Low-Cost Portable Power Supply Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: ADS54RF63EVM
  ADS54RF63 12-Bit, 550-MSPS, RF Sampling Analog-to-Digital Converter Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  

应用须知

• 下载
  Clock jitter analyzed in the time domain, Part 1
  PDF, 302 Kb, 档案已发布: Aug 11, 2010
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  Clock jitter analyzed in the time domain, Part 2
  PDF, 588 Kb, 档案已发布: Nov 15, 2010
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  Clock jitter analyzed in the time domain, Part 3
  PDF, 627 Kb, 档案已发布: Sep 16, 2011
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  4Q 2010 Issue Analog Applications Journal
  PDF, 1.3 Mb, 档案已发布: Nov 15, 2010
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  Signal Chain Noise Figure Analysis
  PDF, 615 Kb, 档案已发布: Oct 29, 2014
• 下载
  3Q 2010 Issue Analog Applications Journal
  PDF, 1.5 Mb, 档案已发布: Aug 11, 2010
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  High-Speed Analog-to-Digital Converter Basics
  PDF, 1.1 Mb, 档案已发布: Jan 11, 2012
  The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil
• 下载
  3Q 2011 Issue Analog Applications Journal
  PDF, 1.4 Mb, 档案已发布: Sep 16, 2011
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  Журнал по применению аналоговых компонентов 3Q 2011
  PDF, 3.9 Mb, 档案已发布: Sep 1, 2011
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  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, 档案已发布: Sep 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
• 下载
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, 档案已发布: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
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  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
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  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, 档案已发布: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
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  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
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  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015

模型线

制造商分类

• Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)