Datasheet Texas Instruments TLE2161AIP — 数据表
| 制造商 | Texas Instruments |
| 系列 | TLE2161A |
| 零件号 | TLE2161AIP |
Excalibur JFET输入高输出驱动uPower运算放大器8-PDIP
数据表
Excalibur JFET-Input High-Output-Drive Micro Power Operational Amplifiers datasheet
PDF, 1.0 Mb, 修订版: D, 档案已发布: May 1, 1996
从文件中提取
价格
状态
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No |
打包
| Pin | 8 |
| Package Type | P |
| Industry STD Term | PDIP |
| JEDEC Code | R-PDIP-T |
| Width (mm) | 6.35 |
| Length (mm) | 9.81 |
| Thickness (mm) | 3.9 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | 下载 |
参数化
| Additional Features | Decompensated Vos Adj Pin |
| Approx. Price (US$) | 0.84 | 1ku |
| Architecture | FET |
| CMRR(Min)(dB) | 72 |
| CMRR(Typ)(dB) | 90 |
| GBW(Typ)(MHz) | 6.4 |
| Input Bias Current(Max)(pA) | 60 |
| Iq per channel(Max)(mA) | 0.35 |
| Iq per channel(Typ)(mA) | 0.29 |
| Number of Channels(#) | 1 |
| Offset Drift(Typ)(uV/C) | 6 |
| Operating Temperature Range(C) | 0 to 70 |
| Output Current(Typ)(mA) | 50 |
| Package Group | SOIC |
| Package Size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Rail-to-Rail | In to V+ |
| Rating | Catalog |
| Slew Rate(Typ)(V/us) | 10 |
| Total Supply Voltage(Max)(+5V=5, +/-5V=10) | 36 |
| Total Supply Voltage(Min)(+5V=5, +/-5V=10) | 7 |
| Vn at 1kHz(Typ)(nV/rtHz) | 40 |
| Vos (Offset Voltage @ 25C)(Max)(mV) | 1.5 |
生态计划
| RoHS | Not Compliant |
| Pb Free | No |
应用须知
- TLE2161 EMI Immunity PerformancePDF, 90 Kb, 档案已发布: Dec 31, 2013
模型线
系列: TLE2161A (6)
- TLE2161ACD TLE2161ACP TLE2161AID TLE2161AIDG4 TLE2161AIDR TLE2161AIP
制造商分类
- Semiconductors > Amplifiers > Operational Amplifiers (Op Amps) > Precision Op Amps