Datasheet Texas Instruments SN74LVTH2952DBLE — 数据表

具有三态输出的3.3V ABT八路总线收发器和寄存器24-SSOP -40至85

数据表

PDF, 849 Kb, 修订版: F, 档案已发布: Oct 10, 2003

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Lifecycle Status	Obsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample Availability	No

Approx. Price (US$)	0.52 \| 1ku
Bits(#)	8
F @ Nom Voltage(Max)(Mhz)	160
ICC @ Nom Voltage(Max)(mA)	0.005
Input Type	TTL/CMOS
Operating Temperature Range(C)	-40 to 85
Output Drive (IOL/IOH)(Max)(mA)	-32/64
Output Type	LVTTL
Package Group	SOIC TSSOP
Package Size: mm2:W x L (PKG)	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) 24SOIC: 160 mm2: 10.3 x 15.5(SOIC)
Rating	Catalog
Schmitt Trigger	No
Technology Family	LVT
VCC(Max)(V)	3.6
VCC(Min)(V)	2.7
Voltage(Nom)(V)	3.3
tpd @ Nom Voltage(Max)(ns)	4.6

RoHS	Not Compliant
Pb Free	No

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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

系列: SN74LVTH2952 (5)

SN74LVTH2952DBLE SN74LVTH2952DW SN74LVTH2952PW SN74LVTH2952PWLE SN74LVTH2952PWR