Datasheet Texas Instruments ADS931E/1K — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADS931 |
| 零件号 | ADS931E/1K |
8位30MSPS模数转换器（ADC）28-SSOP -40至85
数据表
ADS931: SpeedPlus 8-Bit, 30MHz Sampling Analog-To-Digital Converter datasheet
PDF, 436 Kb, 修订版: A, 档案已发布: Feb 23, 2001
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 28 |
| Package Type | DB |
| Industry STD Term | SSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | ADS931E |
| Width (mm) | 5.3 |
| Length (mm) | 10.2 |
| Thickness (mm) | 1.95 |
| Pitch (mm) | .65 |
| Max Height (mm) | 2 |
| Mechanical Data | 下载 |
参数化
| # Input Channels | 1 |
| Analog Input BW | 100 MHz |
| Architecture | Pipeline |
| DNL(Max) | 1 +/-LSB |
| DNL(Typ) | 0.7 +/-LSB |
| ENOB | 7.2 Bits |
| INL(Max) | 2.5 +/-LSB |
| INL(Typ) | 1 +/-LSB |
| Input Buffer | No |
| Input Range | 1,2 Vp-p |
| Interface | Parallel CMOS |
| Operating Temperature Range | -40 to 85 C |
| Package Group | SSOP |
| Package Size: mm2:W x L | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) PKG |
| Power Consumption(Typ) | 69 mW |
| Rating | Catalog |
| Reference Mode | Ext |
| Resolution | 8 Bits |
| SFDR | 49 dB |
| SINAD | 45 dB |
| SNR | 48 dB |
| Sample Rate(Max) | 30 MSPS |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
应用须知
- Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, 档案已发布: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, 档案已发布: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, 档案已发布: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
模型线
制造商分类
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)