Datasheet Texas Instruments ADS8413IRGZRG4 — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADS8413 |
| 零件号 | ADS8413IRGZRG4 |
16位，单极性差分输入，2MSPS采样率，带有LVDS串行接口的4.75V至5.25V ADC 48-VQFN -40至85
数据表
价格
状态
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No |
打包
| Pin | 48 |
| Package Type | RGZ |
| Industry STD Term | VQFN |
| JEDEC Code | S-PQFP-N |
| Width (mm) | 7 |
| Length (mm) | 7 |
| Thickness (mm) | .9 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1 |
| Mechanical Data | 下载 |
参数化
| # Input Channels | 1 |
| Analog Voltage AVDD(Max)(V) | 5.25 |
| Analog Voltage AVDD(Min)(V) | 4.75 |
| Approx. Price (US$) | 21.35 | 1ku |
| Architecture | SAR |
| Digital Supply(Max)(V) | 5.25 |
| Digital Supply(Min)(V) | 2.7 |
| INL(Max)(+/-LSB) | 2 |
| Input Range(Max)(V) | 4.096 |
| Input Type | Differential |
| Integrated Features | Daisy-Chainable Oscillator |
| Interface | Parallel |
| Multi-Channel Configuration | N/A |
| Operating Temperature Range(C) | -40 to 85 |
| Package Group | VQFN |
| Package Size: mm2:W x L (PKG) | 48VQFN: 49 mm2: 7 x 7(VQFN) |
| Power Consumption(Typ)(mW) | 155 |
| Rating | Catalog |
| Reference Mode | Ext Int |
| Resolution(Bits) | 16 |
| SINAD(dB) | 92 |
| SNR(dB) | 92 |
| Sample Rate (max)(SPS) | 2MSPS |
| THD(Typ)(dB) | -107 |
生态计划
| RoHS | Not Compliant |
| Pb Free | No |
应用须知
- Connecting ADS8410/13 With Long CablePDF, 773 Kb, 档案已发布: Dec 2, 2005
Many applications require that the analog-to-digital converter (ADC) be located near the field sensor; however, the digital processing often occurs at a distance. Therefore, the input and output signals need to travel through a long cable from the field sensor to the site where digital processing occurs. This application report is a guide for using a 1-meter cable, the Samtec EQCD Series high data - Using ADS8410/13 in Daisy Chain ModePDF, 3.2 Mb, 档案已发布: May 22, 2006
Many applications require multiple analog-to-digital converters (ADC) in a system. Daisy chaining multiple ADCs enables the use of a single data receiver or a small FPGA. It offers easy and minimal digital routing. This application report describes how multiple ADCs (ADS8410/13) work in a daisy-chain mode. The device offers a high-speed (200 Mbps) LVDS serial interface. This application report als - Using ADS8410/13 in Cascade ModePDF, 2.9 Mb, 档案已发布: Jun 8, 2006
Many applications require multiple analog-to-digital converters (ADC) in a system. Cascading multiple ADCs enables the use of a single data receiver or a small FPGA. This offers lower power consumption and independent ADC usage. This application report describes how multiple ADCs (ADS8410/13) work in a cascade mode. The ADS8410/13 integrated circuit offers a high-speed (200 Mbps) LVDS serial inter - Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, 档案已发布: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
模型线
系列: ADS8413 (7)
- ADS8413IBRGZR ADS8413IBRGZRG4 ADS8413IBRGZT ADS8413IRGZR ADS8413IRGZRG4 ADS8413IRGZT ADS8413IRGZTG4
制造商分类
- Semiconductors > Data Converters > Analog to Digital Converter > Precision ADC (<=10MSPS)