Datasheet Texas Instruments ADS8472IBRGZTG4 — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADS8472 |
| 零件号 | ADS8472IBRGZTG4 |
具有并行接口和参考电压48-VQFN的16位1MSPS 0.65 LSB最大INL精密ADC -40至85
数据表
16-Bit 1-MSPS Differential Input, Micropower Samp Analog-to-Digital Converter datasheet
PDF, 1.4 Mb, 档案已发布: Sep 27, 2006
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 48 | 48 | 48 |
| Package Type | RGZ | RGZ | RGZ |
| Industry STD Term | VQFN | VQFN | VQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N | S-PQFP-N |
| Package QTY | 250 | 250 | 250 |
| Carrier | SMALL T&R | SMALL T&R | SMALL T&R |
| Device Marking | ADS | 8472I | B |
| Width (mm) | 7 | 7 | 7 |
| Length (mm) | 7 | 7 | 7 |
| Thickness (mm) | .9 | .9 | .9 |
| Pitch (mm) | .5 | .5 | .5 |
| Max Height (mm) | 1 | 1 | 1 |
| Mechanical Data | 下载 | 下载 | 下载 |
参数化
| # Input Channels | 1 |
| Analog Voltage AVDD(Max) | 5.25 V |
| Analog Voltage AVDD(Min) | 4.75 V |
| Architecture | SAR |
| Digital Supply(Max) | 5.25 V |
| Digital Supply(Min) | 2.7 V |
| INL(Max) | 0.65 +/-LSB |
| Input Range(Max) | 4.096 V |
| Input Range(Min) | 4.096 V |
| Input Type | Differential |
| Integrated Features | Oscillator |
| Interface | Parallel |
| Multi-Channel Configuration | N/A |
| Operating Temperature Range | -40 to 85 C |
| Package Group | VQFN |
| Package Size: mm2:W x L | 48VQFN: 49 mm2: 7 x 7(VQFN) PKG |
| Power Consumption(Typ) | 225 mW |
| Rating | Catalog |
| Reference Mode | Ext,Int |
| Resolution | 16 Bits |
| SINAD | 95.2 dB |
| SNR | 95.3 dB |
| Sample Rate (max) | 1MSPS SPS |
| Sample Rate(Max) | 1 MSPS |
| THD(Typ) | -121 dB |
生态计划
| RoHS | Compliant |
应用须知
- Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, 档案已发布: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
模型线
系列: ADS8472 (4)
- ADS8472IBRGZT ADS8472IBRGZTG4 ADS8472IRGZT ADS8472IRGZTG4
制造商分类
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)