SM320C6472-HiRel
www.ti.com SPRS696B – SEPTEMBER 2010 – REVISED OCTOBER 2010 SM320C6472 Fixed-Point Digital Signal Processor
1 Features Congestion Control IEEE 1149.6 Compliant I/Os
– UTOPIA UTOPIA Level 2 Slave ATM Controller 8/16-Bit Transmit and Receive
Operations up to 50 MHz per Direction User-Defined Cell Format up to 64 Bytes
– Two 10/100/1000 Mb/s Ethernet MACs
(EMACs) Both EMACs are IEEE 802.3 Compliant EMAC0 Supports:
– MII, RMII, SS-SMII, GMII, and RGMII
– 8 Independent Transmit (TX)
Channels
– 8 Independent Receive (RX)
Channels EMAC1 Supports:
– RMII, SS-SMII and RGMII
– 8 Independent Transmit (TX)
Channels
– 8 Independent Receive (RX)
Channels Both EMACs (EMAC0 and EMAC1) Share
MDIO Interface
– 16-Bit Host-Port Interface (HPI)
– One Inter-Integrated Circuit (I2C) Bus
– Six Shared 64-Bit General-Purpose Timers
System PLL and PLL Controller
Secondary PLL and PLL Controller, Dedicated …
