Datasheet Texas Instruments OPA842IDRG4 — 数据表
| 制造商 | Texas Instruments |
| 系列 | OPA842 |
| 零件号 | OPA842IDRG4 |
宽带，低失真，单位增益稳定，电压反馈运算放大器8-SOIC -40至85
数据表
Wideband Low Distortion Unity-Gain Stable Voltage-Feedback Op Amp datasheet
PDF, 813 Kb, 修订版: D, 档案已发布: Sep 28, 2010
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 8 | 8 |
| Package Type | D | D |
| Industry STD Term | SOIC | SOIC |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Package QTY | 2500 | 2500 |
| Carrier | LARGE T&R | LARGE T&R |
| Device Marking | 842 | OPA |
| Width (mm) | 3.91 | 3.91 |
| Length (mm) | 4.9 | 4.9 |
| Thickness (mm) | 1.58 | 1.58 |
| Pitch (mm) | 1.27 | 1.27 |
| Max Height (mm) | 1.75 | 1.75 |
| Mechanical Data | 下载 | 下载 |
参数化
| 2nd Harmonic | 80 dBc |
| 3rd Harmonic | 97 dBc |
| @ MHz | 5 |
| Acl, min spec gain | 1 V/V |
| Additional Features | N/A |
| Architecture | Bipolar,Voltage FB |
| BW @ Acl | 350 MHz |
| CMRR(Min) | 85 dB |
| CMRR(Typ) | 95 dB |
| GBW(Typ) | 350 MHz |
| Input Bias Current(Max) | 35000000 pA |
| Iq per channel(Max) | 20.8 mA |
| Iq per channel(Typ) | 20.2 mA |
| Number of Channels | 1 |
| Offset Drift(Typ) | 4 uV/C |
| Operating Temperature Range | -40 to 85 C |
| Output Current(Typ) | 100 mA |
| Package Group | SOIC |
| Package Size: mm2:W x L | 8SOIC: 29 mm2: 6 x 4.9(SOIC) PKG |
| Rail-to-Rail | No |
| Rating | Catalog |
| Slew Rate(Typ) | 400 V/us |
| Total Supply Voltage(Max) | 12 +5V=5, +/-5V=10 |
| Total Supply Voltage(Min) | 7 +5V=5, +/-5V=10 |
| Vn at 1kHz(Typ) | 2.6 nV/rtHz |
| Vn at Flatband(Typ) | 2.7 nV/rtHz |
| Vos (Offset Voltage @ 25C)(Max) | 1.2 mV |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- Evaluation Modules & Boards: DEM-OPA-SOT-1A
Unpopulated PCB Compatible w/High Speed, Wide Bandwidth Op Amps in SOT(DBV) Pkg
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: DEM-OPA-SO-1A
DEM-OPA-SO-1A Unpopulated PCB Compatible w/High Speed Wide Bandwidth Op Amps in 8-lead SOIC (D) Pkg
Lifecycle Status: Active (Recommended for new designs)
应用须知
- RLC Filter Design for ADC Interface Applications (Rev. A)PDF, 299 Kb, 修订版: A, 档案已发布: May 13, 2015
As high performance Analog-to-Digital Converters (ADCs) continue to improve in their performance, the last stage interface from the final amplifier into the converter inputs becomes a critical element in the system design if the full converter dynamic range is desired. This application note describes the performance and design equations for a simple passive 2nd-order filter used successfully in AD - ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC DriversPDF, 273 Kb, 档案已发布: Apr 22, 2004
Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation - Wideband Complementary Current Output DAC Single-Ended InterfacePDF, 597 Kb, 档案已发布: Jun 21, 2005
High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA - Measuring Board Parasitics in High-Speed Analog DesignPDF, 134 Kb, 档案已发布: Jul 7, 2003
Successful circuit designs using high-speed amplifiers can depend upon understanding and identifying parasitic PCB components. Simulating a design while including PCB parasitics can protect against unpleasant production surprises. This application report discusses an easy method for measuring parasitic components in a prototype or final PC board design by using a standard oscilloscope and low freq - Noise Analysis for High Speed Op Amps (Rev. A)PDF, 256 Kb, 修订版: A, 档案已发布: Jan 17, 2005
As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu
模型线
系列: OPA842 (8)
制造商分类
- Semiconductors > Amplifiers > Operational Amplifiers (Op Amps) > High-Speed Op Amps (>=50MHz)