Datasheet Texas Instruments 66AK2L06XCMSA — 数据表
| 制造商 | Texas Instruments |
| 系列 | 66AK2L06 |
| 零件号 | 66AK2L06XCMSA |
多核DSP + ARM KeyStone II片上系统（SoC）900-FCBGA -40至100
数据表
66AK2L06 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) datasheet
PDF, 1.9 Mb, 档案已发布: Apr 21, 2015
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
打包
| Pin | 900 | 900 | 900 |
| Package Type | CMS | CMS | CMS |
| Package QTY | 44 | 44 | 44 |
| Device Marking | A1GHZ | @2013 | 66AK2L06XCMS |
| Width (mm) | 25 | 25 | 25 |
| Length (mm) | 25 | 25 | 25 |
| Thickness (mm) | 2.98 | 2.98 | 2.98 |
| Mechanical Data | 下载 | 下载 | 下载 |
参数化
| ARM CPU | 2 ARM Cortex-A15 |
| ARM MHz | 1200 Max. |
| Applications | Avionics and Defense,Medical,Test and Measurement |
| DRAM | DDR3,DDR3L |
| DSP | 4 C66x |
| DSP MHz | 1200 Max. |
| EMAC | 4-port 1Gb Switch |
| Hardware Accelerators | FFT Coprocessor,Digital Front End |
| I2C | 3 |
| JESD204B | 4 Lanes |
| On-Chip L2 Cache | 1024 KB (ARM Cluster),1024 KB (per C66x DSP core) |
| Operating Systems | Integrity,Linux,SYS/BIOS,VxWorks |
| Operating Temperature Range | -40 to 100,0 to 100 C |
| Other On-Chip Memory | 3072 KB |
| PCI/PCIe | 2 PCIe Gen2 |
| Rating | Catalog |
| SPI | 3 |
| UART | 4 SCI |
| USB | 1 |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU200-U
XDS200 USB Debug Probe
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: XEVMK2LX
66AK2L06 Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
应用须知
- TPS544Bxx/TPS544Cxx Powering TCI6630K2L in Smart Reflex Class 0 TC ModePDF, 154 Kb, 档案已发布: Sep 18, 2015
This application report describes an application circuit example of the TPS544B/Cxx family of power management IC (PMIC) powering the Smart-Reflex digital core supply of the TCI6630K2L SoC. Smart-Reflex Class 0 Temperature Compensation (Class 0 TC) mode of operation of the TCI6630K2L device is emphasized. Assumption is that temperature compensation mode is enabled using the function provided in th - 66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B)PDF, 8.8 Mb, 修订版: B, 档案已发布: Jun 20, 2016
- Keystone EDMA FAQPDF, 1.3 Mb, 档案已发布: Sep 1, 2016
This document is a collection of frequently asked questions (FAQs) on enhanced direct memory access (EDMA) on KeyStoneв„ў I (KS1) and KeyStone II (KS2) devices, along with useful collateral and software reference links. - System solution for avionics & defensePDF, 1.2 Mb, 档案已发布: Sep 23, 2015
- Keystone II DDR3 InitializationPDF, 73 Kb, 档案已发布: Jan 26, 2015
This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller. - Power Management of KS2 Device (Rev. C)PDF, 61 Kb, 修订版: C, 档案已发布: Jul 15, 2016
This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices. - Throughput Performance Guide for KeyStone II Devices (Rev. B)PDF, 866 Kb, 修订版: B, 档案已发布: Dec 22, 2015
This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access. - Keystone II DDR3 Debug GuidePDF, 143 Kb, 档案已发布: Oct 16, 2015
This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device. - Hardware Design Guide for KeyStone II DevicesPDF, 1.8 Mb, 档案已发布: Mar 24, 2014
- SERDES Link Commissioning on KeyStone I and II DevicesPDF, 138 Kb, 档案已发布: Apr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices. - PCIe Use Cases for KeyStone DevicesPDF, 320 Kb, 档案已发布: Dec 13, 2011
- Optimizing Loops on the C66x DSPPDF, 585 Kb, 档案已发布: Nov 9, 2010
- The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)PDF, 20 Kb, 修订版: A, 档案已发布: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM - Clocking Design Guide for KeyStone DevicesPDF, 1.5 Mb, 档案已发布: Nov 9, 2010
- DDR3 Design Requirements for KeyStone Devices (Rev. B)PDF, 582 Kb, 修订版: B, 档案已发布: Jun 5, 2014
- Multicore Programming Guide (Rev. B)PDF, 1.8 Mb, 修订版: B, 档案已发布: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore - TI DSP BenchmarkingPDF, 62 Kb, 档案已发布: Jan 13, 2016
This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.
模型线
系列: 66AK2L06 (4)
- 66AK2L06XCMS 66AK2L06XCMS2 66AK2L06XCMSA 66AK2L06XCMSA2
制造商分类
- Semiconductors > Processors > Digital Signal Processors > C6000 DSP + ARM Processors > 66AK2x