Datasheet Texas Instruments ADS805U/1K — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADS805 |
| 零件号 | ADS805U/1K |
12位，20 MSPS ADC内部/外部基准电压，2至5Vpp之间的灵活I / P，超出范围指示器，引脚补偿。 28-SOIC -40至85
数据表
12-Bit, 20MHz Sampling Analog-To-Digital Converter datasheet
PDF, 812 Kb, 修订版: B, 档案已发布: Jul 18, 2002
从文件中提取
价格
状态
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No |
打包
| Pin | 28 |
| Package Type | DW |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Width (mm) | 7.5 |
| Length (mm) | 17.9 |
| Thickness (mm) | 2.35 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.65 |
| Mechanical Data | 下载 |
替代品
| Replacement | ADS805E/1K |
| Replacement Code | F |
参数化
| # Input Channels | 1 |
| Analog Input BW(MHz) | 270 |
| Approx. Price (US$) | 11.95 | 1ku |
| Architecture | Pipeline |
| DNL(Max)(+/-LSB) | 0.75 |
| ENOB(Bits) | 0.25 |
| INL(Max)(+/-LSB) | 1 |
| Input Buffer | No |
| Input Range | 2V / 5V(p-p) |
| Interface | Parallel CMOS |
| Operating Temperature Range(C) | -40 to 85 |
| Package Group | SSOP |
| Package Size: mm2:W x L (PKG) | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) |
| Power Consumption(Typ)(mW) | 300 |
| Rating | Catalog |
| Reference Mode | Ext Int |
| Resolution(Bits) | 12 |
| SFDR(dB) | 74 |
| SINAD(dB) | 66 |
| SNR(dB) | 68 |
| Sample Rate(Max)(MSPS) | 20 |
生态计划
| RoHS | Not Compliant |
| Pb Free | No |
设计套件和评估模块
- Evaluation Modules & Boards: TSW2200EVM
TSW2200EVM: Low Cost Portable Power Supply
Lifecycle Status: Active (Recommended for new designs)
应用须知
- Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Interleaving Analog-to-Digital ConvertersPDF, 64 Kb, 档案已发布: Oct 2, 2000
It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, 档案已发布: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - What Designers Should Know About Data Converter DriftPDF, 95 Kb, 档案已发布: Oct 2, 2000
Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify. - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
- CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, 档案已发布: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, 档案已发布: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
模型线
系列: ADS805 (5)
- ADS805E ADS805E/1K ADS805EG4 ADS805U ADS805U/1K
制造商分类
- Semiconductors > Data Converters > Analog to Digital Converter > High Speed ADC (>10MSPS)