Datasheet Texas Instruments ADS8363SRHBT — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADS8363 |
| 零件号 | ADS8363SRHBT |
16位，1-MSPS，4x2 / 2x2同步采样SAR ADC 32-VQFN -40至125
数据表
ADSxxx3 Dual, 1-MSPS, 16-, 14-, and 12-Bit, 4Г—2 or 2Г—2 Channel, Simultaneous Sampling Analog-to-Digital Converter datasheet
PDF, 1.4 Mb, 修订版: D, 档案已发布: Sep 2, 2017
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价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
打包
| Pin | 32 |
| Package Type | RHB |
| Industry STD Term | VQFN |
| JEDEC Code | S-PQFP-N |
| Package QTY | 250 |
| Carrier | SMALL T&R |
| Device Marking | ADS8363 |
| Width (mm) | 5 |
| Length (mm) | 5 |
| Thickness (mm) | .9 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1 |
| Mechanical Data | 下载 |
参数化
| # Input Channels | 4 |
| Analog Voltage AVDD(Max) | 5.5 V |
| Analog Voltage AVDD(Min) | 2.7 V |
| Architecture | SAR |
| Digital Supply(Max) | 5.5 V |
| Digital Supply(Min) | 2.3 V |
| INL(Max) | 3 +/-LSB |
| Input Range(Max) | 5.5 V |
| Input Type | Differential,Pseudo-Differential |
| Integrated Features | N/A |
| Interface | SPI |
| Multi-Channel Configuration | Multiplexed,Simultaneous Sampling |
| Operating Temperature Range | -40 to 125 C |
| Package Group | VQFN |
| Package Size: mm2:W x L | 32VQFN: 25 mm2: 5 x 5(VQFN) PKG |
| Power Consumption(Typ) | 47.2 mW |
| Rating | Catalog |
| Reference Mode | Ext,Int |
| Resolution | 16 Bits |
| SINAD | 92 dB |
| SNR | 93 dB |
| Sample Rate (max) | 1MSPS SPS |
| Sample Rate(Max) | 1 MSPS |
| THD(Typ) | -98 dB |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- Evaluation Modules & Boards: ADS8363EVM
ADS8363 Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
应用须知
- Using the Sequencer and Pseudo-Differential Features of the ADS8363PDF, 161 Kb, 档案已发布: May 21, 2014
- Interfacing to the ADS8363 Pseudo-Differential Operating ModePDF, 548 Kb, 档案已发布: Aug 4, 2014
- Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, 档案已发布: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
模型线
系列: ADS8363 (2)
- ADS8363SRHBR ADS8363SRHBT
制造商分类
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)