Datasheet Texas Instruments TLC2652IP — 数据表

稳定斩波稳定的运算放大器8-PDIP

数据表

PDF, 1.1 Mb, 修订版: E, 档案已发布: Feb 9, 2005

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Additional Features	Zero Drift
Architecture	CMOS
CMRR(Min)	120 dB
CMRR(Typ)	140 dB
GBW(Typ)	1.9 MHz
Input Bias Current(Max)	60 pA
Iq per channel(Max)	2.4 mA
Iq per channel(Typ)	1.5 mA
Number of Channels	1
Offset Drift(Typ)	0.01 uV/C
Operating Temperature Range	-40 to 125 C
Output Current(Typ)	3 mA
Package Group	PDIP
Package Size: mm2:W x L	See datasheet (PDIP) PKG
Rail-to-Rail	In to V-,Out
Rating	Catalog
Slew Rate(Typ)	2.8 V/us
Total Supply Voltage(Max)	16 +5V=5, +/-5V=10
Total Supply Voltage(Min)	3.8 +5V=5, +/-5V=10
Vn at 1kHz(Typ)	23 nV/rtHz
Vos (Offset Voltage @ 25C)(Max)	0.003 mV

RoHS	Compliant
Pb Free	Yes

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系列: TLC2652 (13)

Semiconductors > Amplifiers > Operational Amplifiers (Op Amps) > Precision Op Amps