Datasheet Texas Instruments ADS7881IRGZR — 数据表

制造商	Texas Instruments
系列	ADS7881
零件号	ADS7881IRGZR

具有Ref 48-VQFN -40至85的2.7V-5.25V数字，5V模拟，12位，4MSPS，并行ADC

数据表

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PDF, 1.0 Mb, 修订版: B, 档案已发布: Nov 11, 2005

从文件中提取

价格

状态

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

打包

Pin	48	48
Package Type	RGZ	RGZ
Industry STD Term	VQFN	VQFN
JEDEC Code	S-PQFP-N	S-PQFP-N
Package QTY	2500	2500
Carrier	LARGE T&R	LARGE T&R
Device Marking	7881I	ADS
Width (mm)	7	7
Length (mm)	7	7
Thickness (mm)	.9	.9
Pitch (mm)	.5	.5
Max Height (mm)	1	1
Mechanical Data	下载	下载

参数化

# Input Channels	1
Analog Voltage AVDD(Max)(V)	5.25
Analog Voltage AVDD(Min)(V)	4.75
Approx. Price (US$)	7.35 \| 1ku
Architecture	SAR
Digital Supply(Max)(V)	5.25
Digital Supply(Min)(V)	2.7
INL(Max)(+/-LSB)	1
Input Range(Max)(V)	2.6
Input Type	Pseudo-Differential Single-Ended
Integrated Features	Oscillator
Interface	Parallel
Multi-Channel Configuration	N/A
Operating Temperature Range(C)	-40 to 85
Package Group	VQFN
Package Size: mm2:W x L (PKG)	48VQFN: 49 mm2: 7 x 7(VQFN)
Power Consumption(Typ)(mW)	95
Rating	Catalog
Reference Mode	Ext Int
Resolution(Bits)	12
SINAD(dB)	71.5
SNR(dB)	71.5
Sample Rate (max)(SPS)	4MSPS
THD(Typ)(dB)	-91

生态计划

RoHS	Compliant
Pb Free	Yes

设计套件和评估模块

Evaluation Modules & Boards: ADS7881EVM
ADS7881EVM Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
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应用须知

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Interfacing the ADS7881 to TMS320C6713 DSP
PDF, 1.1 Mb, 档案已发布: Jun 30, 2005
This application report presents a solution to interfacing the ADS7881 12-bit parallel interface converter to the TMS320C6713 DSP. The hardware solution is made up of existing hardware, specifically, the ADS7881EVM, 'C6713 DSK, and the 5-6K Interface Board. The software demonstrates how to use an EDMA ping-pong buffer and Timer1 peripherals to collect data at 4 MSPS. Discussed also are some of the
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Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
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Determining Minimum Acquisition Times for SAR ADCs, part 2
PDF, 215 Kb, 档案已发布: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
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Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
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A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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Principles of Data Acquisition and Conversion (Rev. A)
PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015

模型线

系列: ADS7881 (4)

ADS7881IPFBR ADS7881IPFBT ADS7881IRGZR ADS7881IRGZT

制造商分类

Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)