Datasheet Texas Instruments TMS320DM369ZCE — 数据表

制造商Texas Instruments
系列TMS320DM369
零件号TMS320DM369ZCE
Datasheet Texas Instruments TMS320DM369ZCE

达芬奇数字媒体处理器338-NFBGA 0至85

数据表

TMS320DM369 Digital Media System-on-Chip (DMSoC) datasheet
PDF, 1.5 Mb, 修订版: A, 档案已发布: Jul 12, 2016
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

Pin338338
Package TypeZCEZCE
Industry STD TermNFBGANFBGA
JEDEC CodeS-PBGA-NS-PBGA-N
Package QTY160160
CarrierJEDEC TRAY (5+1)JEDEC TRAY (5+1)
Device Marking570DM369ZCE
Width (mm)1313
Length (mm)1313
Thickness (mm).89.89
Pitch (mm).65.65
Max Height (mm)1.31.3
Mechanical Data下载下载

参数化

ARM CPU1 ARM9
ARM MHz432 Max.
ApplicationsConsumer Electronics,Industrial Cameras,Security, Video and Imaging, Portable Cameras,Video Surveillance IP Cameras
DRAMLPDDR,DDR2
EMAC10/100
I2C1
Operating SystemsLinux
Operating Temperature Range-40 to 85,0 to 85 C
Pin/Package338NFBGA
RatingCatalog
SPI5
UART2 SCI
USBUSB2.0 HS OTG
Video Acceleration1 MJCP,1 HDVICP
Video Port1 Dedicated Input,1 Dedicated Output Configurable
Video Resolution/Frame Rate1080P,30 FPS or less

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: TMDXEVM368
    TMS320DM36x Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • TMS320DM36x SoC Architecture and Throughput
    PDF, 5.8 Mb, 档案已发布: Jul 29, 2009
    This application report provides information on the DM36x throughput performance and describes the DM36x System-on-Chip (SoC) architecture, data path infrastructure, and constraints that affect the throughput and different optimization techniques for optimum system performance. This document also provides information on the maximum possible throughput performance of different peripherals on the So
  • Converting single-ended video to differential video in single-supply systems
    PDF, 212 Kb, 档案已发布: Sep 16, 2011
  • Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A)
    PDF, 93 Kb, 修订版: A, 档案已发布: Jul 17, 2008
    This application report motivates the way the DDR high-speed timing requirements are now going to be communicated to system designers. The traditional method of using data sheet parameters and simulation models is tedious. The system designer uses this information to evaluate whether timing specifications are met and can be expected to operate reliably.Ultimately, the real question the hardwa
  • High-Speed Interface Layout Guidelines (Rev. G)
    PDF, 814 Kb, 修订版: G, 档案已发布: Jul 27, 2017
    As modern bus interface frequencies scale higher, care must be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust solution.

模型线

制造商分类

  • Semiconductors > Processors > Digital Signal Processors > Media Processors > Digital Video Processors