Datasheet Texas Instruments 74AC11032 — 数据表

制造商Texas Instruments
系列74AC11032
Datasheet Texas Instruments 74AC11032

四路2输入正或门

数据表

Quadruple 2-Input Positive-OR Gate datasheet
PDF, 1.4 Mb, 修订版: C, 档案已发布: Apr 1, 1996
从文件中提取

价格

状态

74AC11032D74AC11032DBLE74AC11032DBR74AC11032DE474AC11032DRE474AC11032N74AC11032NSR
Lifecycle StatusActive (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNo

打包

74AC11032D74AC11032DBLE74AC11032DBR74AC11032DE474AC11032DRE474AC11032N74AC11032NSR
N1234567
Pin16161616161616
Package TypeDDBDBDDNNS
Industry STD TermSOICSSOPSSOPSOICSOICPDIPSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDIP-TR-PDSO-G
Package QTY40200040252000
CarrierTUBELARGE T&RTUBETUBELARGE T&R
Device MarkingAC11032AE032AC1103274AC11032NAC11032
Width (mm)3.915.35.33.913.916.355.3
Length (mm)9.96.26.29.99.919.310.3
Thickness (mm)1.581.951.951.581.583.91.95
Pitch (mm)1.27.65.651.271.272.541.27
Max Height (mm)1.75221.751.755.082
Mechanical Data下载下载下载下载下载下载下载

参数化

Parameters / Models74AC11032D
74AC11032D
74AC11032DBLE
74AC11032DBLE
74AC11032DBR
74AC11032DBR
74AC11032DE4
74AC11032DE4
74AC11032DRE4
74AC11032DRE4
74AC11032N
74AC11032N
74AC11032NSR
74AC11032NSR
Approx. Price (US$)0.94 | 1ku0.94 | 1ku
Bits44444
Bits(#)44
F @ Nom Voltage(Max), Mhz100100100100100
F @ Nom Voltage(Max)(Mhz)100100
ICC @ Nom Voltage(Max), mA0.040.040.040.040.04
ICC @ Nom Voltage(Max)(mA)0.040.04
Input TypeCMOS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-24
Output Drive (IOL/IOH)(Max)(mA)24/-2424/-24
Output TypeCMOS
Package GroupSOICSSOPSSOPSOICSOICPDIPSO
Package Size: mm2:W x L, PKG16SOIC: 59 mm2: 6 x 9.9(SOIC)16SSOP: 48 mm2: 7.8 x 6.2(SSOP)16SOIC: 59 mm2: 6 x 9.9(SOIC)See datasheet (PDIP)16SO: 80 mm2: 7.8 x 10.2(SO)
Package Size: mm2:W x L (PKG)See datasheet (PDIP)See datasheet (PDIP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNo
Technology FamilyACACACACACACAC
VCC(Max), V5.55.55.55.55.5
VCC(Max)(V)5.55.5
VCC(Min), V33333
VCC(Min)(V)33
Voltage(Nom), V3.3,53.3,53.3,53.3,53.3,5
Voltage(Nom)(V)3.3
5
3.3
5
tpd @ Nom Voltage(Max), ns9.7,6.79.7,6.79.7,6.79.7,6.79.7,6.7
tpd @ Nom Voltage(Max)(ns)9.7
6.7
9.7
6.7

生态计划

74AC11032D74AC11032DBLE74AC11032DBR74AC11032DE474AC11032DRE474AC11032N74AC11032NSR
RoHSCompliantNot CompliantCompliantCompliantNot CompliantCompliantCompliant
Pb FreeNoYesNo

应用须知

  • Live Insertion
    PDF, 150 Kb, 档案已发布: Oct 1, 1996
    Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance and repair. To avoid damaging components additional circuitry modifications are necessary. This document describes in detail the phenomena tha
  • Introduction to Logic
    PDF, 93 Kb, 档案已发布: Apr 30, 2015
  • Implications of Slow or Floating CMOS Inputs (Rev. D)
    PDF, 260 Kb, 修订版: D, 档案已发布: Jun 23, 2016
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, 修订版: C, 档案已发布: Dec 2, 2015
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, 档案已发布: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • TI IBIS File Creation Validation and Distribution Processes
    PDF, 380 Kb, 档案已发布: Aug 29, 2002
    The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
  • CMOS Power Consumption and CPD Calculation (Rev. B)
    PDF, 89 Kb, 修订版: B, 档案已发布: Jun 1, 1997
    Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
  • Input and Output Characteristics of Digital Integrated Circuits
    PDF, 1.7 Mb, 档案已发布: Oct 1, 1996
    This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou
  • Designing With Logic (Rev. C)
    PDF, 186 Kb, 修订版: C, 档案已发布: Jun 1, 1997
    Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, 档案已发布: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
  • Shelf-Life Evaluation of Lead-Free Component Finishes
    PDF, 1.3 Mb, 档案已发布: May 24, 2004
    The integrated circuit (IC) industry is converting to lead (Pb)-free termination finishes for leadframe-based packages. IC component users need to know the maximum length of time that components can be stored prior to being soldered. This study predicts shelf life of the primary Pb-free finishes being proposed by the industry. Components were exposed to a controlled environment, with known aging a

模型线

制造商分类

  • Semiconductors> Logic> Gate> OR Gate