Datasheet Texas Instruments 74ACT11657 — 数据表
| 制造商 | Texas Instruments |
| 系列 | 74ACT11657 |
八路奇偶校验总线收发器
数据表
Octal Transceiver With Parity Generator/Checker And 3-State Outputs
PDF, 115 Kb, 档案已发布: Apr 1, 1993
价格
状态
| 74ACT11657DW | 74ACT11657DWR | |
|---|---|---|
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No | No |
打包
| 74ACT11657DW | 74ACT11657DWR | |
|---|---|---|
| N | 1 | 2 |
| Pin | 28 | 28 |
| Package Type | DW | DW |
| Industry STD Term | SOIC | SOIC |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Width (mm) | 7.5 | 7.5 |
| Length (mm) | 17.9 | 17.9 |
| Thickness (mm) | 2.35 | 2.35 |
| Pitch (mm) | 1.27 | 1.27 |
| Max Height (mm) | 2.65 | 2.65 |
| Mechanical Data | 下载 | 下载 |
生态计划
| 74ACT11657DW | 74ACT11657DWR | |
|---|---|---|
| RoHS | Not Compliant | Not Compliant |
| Pb Free | No | No |
应用须知
- Selecting the Right Level Translation Solution (Rev. A)PDF, 313 Kb, 修订版: A, 档案已发布: Jun 22, 2004
Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati - Implications of Slow or Floating CMOS Inputs (Rev. D)PDF, 260 Kb, 修订版: D, 档案已发布: Jun 23, 2016
- TI IBIS File Creation Validation and Distribution ProcessesPDF, 380 Kb, 档案已发布: Aug 29, 2002
The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con - CMOS Power Consumption and CPD Calculation (Rev. B)PDF, 89 Kb, 修订版: B, 档案已发布: Jun 1, 1997
Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale - Designing With Logic (Rev. C)PDF, 186 Kb, 修订版: C, 档案已发布: Jun 1, 1997
Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w - Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, 档案已发布: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
模型线
系列: 74ACT11657 (2)
制造商分类
- Semiconductors> Logic> Buffer/Driver/Transceiver> Parity Transceiver