Datasheet Texas Instruments ADS41B25 — 数据表
制造商 | Texas Instruments |
系列 | ADS41B25 |
12位125MSPS模数转换器(ADC)
数据表
12-Bit, 125MSPS Ultra-Low Power ADC with Analog Buffer datasheet
PDF, 1.6 Mb, 档案已发布: Jun 22, 2011
从文件中提取
价格
状态
ADS41B25IRGZR | ADS41B25IRGZT | |
---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | No | Yes |
打包
ADS41B25IRGZR | ADS41B25IRGZT | |
---|---|---|
N | 1 | 2 |
Pin | 48 | 48 |
Package Type | RGZ | RGZ |
Industry STD Term | VQFN | VQFN |
JEDEC Code | S-PQFP-N | S-PQFP-N |
Package QTY | 2500 | 250 |
Carrier | LARGE T&R | SMALL T&R |
Device Marking | AZ41B25 | AZ41B25 |
Width (mm) | 7 | 7 |
Length (mm) | 7 | 7 |
Thickness (mm) | .9 | .9 |
Pitch (mm) | .5 | .5 |
Max Height (mm) | 1 | 1 |
Mechanical Data | 下载 | 下载 |
参数化
Parameters / Models | ADS41B25IRGZR | ADS41B25IRGZT |
---|---|---|
# Input Channels | 1 | 1 |
Analog Input BW, MHz | 800 | 800 |
Architecture | Pipeline | Pipeline |
DNL(Typ), +/-LSB | 1.5 | 1.5 |
ENOB, Bits | 11.1 | 11.1 |
INL(Max), +/-LSB | 3.5 | 3.5 |
INL(Typ), +/-LSB | 1.5 | 1.5 |
Input Buffer | Yes | Yes |
Input Range, Vp-p | 1.5 | 1.5 |
Interface | DDR LVDS,Parallel CMOS | DDR LVDS,Parallel CMOS |
Operating Temperature Range, C | -40 to 85 | -40 to 85 |
Package Group | VQFN | VQFN |
Package Size: mm2:W x L, PKG | 48VQFN: 49 mm2: 7 x 7(VQFN) | 48VQFN: 49 mm2: 7 x 7(VQFN) |
Power Consumption(Typ), mW | 310 | 310 |
Rating | Catalog | Catalog |
Reference Mode | Int | Int |
Resolution, Bits | 12 | 12 |
SFDR, dB | 89 | 89 |
SINAD, dB | 68.8 | 68.8 |
SNR, dB | 68.8 | 68.8 |
Sample Rate(Max), MSPS | 125 | 125 |
生态计划
ADS41B25IRGZR | ADS41B25IRGZT | |
---|---|---|
RoHS | Compliant | Compliant |
应用须知
- High-Speed Analog-to-Digital Converter BasicsPDF, 1.1 Mb, 档案已发布: Jan 11, 2012
The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil - Band-Pass Filter Design Techniques for High-Speed ADCsPDF, 733 Kb, 档案已发布: Feb 27, 2012
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TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, 修订版: A, 档案已发布: Jul 19, 2013
- Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, 修订版: A, 档案已发布: May 22, 2015
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, 档案已发布: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
模型线
系列: ADS41B25 (2)
制造商分类
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)