Datasheet Texas Instruments ADS42JB69 — 数据表

制造商Texas Instruments
系列ADS42JB69
Datasheet Texas Instruments ADS42JB69

双通道,16位,250MSPS模数转换器(ADC)

数据表

ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters datasheet
PDF, 5.3 Mb, 修订版: F, 档案已发布: Dec 22, 2014
从文件中提取

价格

状态

ADS42JB69IRGC25ADS42JB69IRGCRADS42JB69IRGCT
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoYesNo

打包

ADS42JB69IRGC25ADS42JB69IRGCRADS42JB69IRGCT
N123
Pin646464
Package TypeRGCRGCRGC
Industry STD TermVQFNVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-NS-PQFP-N
Package QTY252000250
CarrierSMALL T&RLARGE T&RSMALL T&R
Device MarkingAZ42JB69AZ42JB69AZ42JB69
Width (mm)999
Length (mm)999
Thickness (mm).88.88.88
Pitch (mm).5.5.5
Max Height (mm)111
Mechanical Data下载下载下载

参数化

Parameters / ModelsADS42JB69IRGC25
ADS42JB69IRGC25
ADS42JB69IRGCR
ADS42JB69IRGCR
ADS42JB69IRGCT
ADS42JB69IRGCT
# Input Channels222
Analog Input BW, MHz900900900
ArchitecturePipelinePipelinePipeline
DNL(Max), +/-LSB0.60.60.6
DNL(Typ), +/-LSB0.60.60.6
ENOB, Bits12.312.312.3
INL(Max), +/-LSB333
INL(Typ), +/-LSB333
Input BufferYesYesYes
Input Range, Vp-p2.52.52.5
InterfaceJESD204BJESD204BJESD204B
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Package GroupVQFNVQFNVQFN
Package Size: mm2:W x L, PKG64VQFN: 81 mm2: 9 x 9(VQFN)64VQFN: 81 mm2: 9 x 9(VQFN)64VQFN: 81 mm2: 9 x 9(VQFN)
Power Consumption(Typ), mW170017001700
RatingCatalogCatalogCatalog
Reference ModeIntIntInt
Resolution, Bits161616
SFDR, dB959595
SINAD, dB75.775.775.7
SNR, dB75.975.975.9
Sample Rate(Max), MSPS250250250

生态计划

ADS42JB69IRGC25ADS42JB69IRGCRADS42JB69IRGCT
RoHSCompliantCompliantCompliant

应用须知

  • Correcting the Low-Frequency Response of the ADS42LBxx, ADS42JBxx for Time-Domai
    PDF, 338 Kb, 档案已发布: May 2, 2016
    In this application report, simple schemes are described to correct the low-frequency response of ADS42LBxx, ADS42JBxx family of analog-to-digital converters (ADCs). The described schemes are useful for time-domain applications where the ADC samples a low-frequency pulse signal. These schemes are simple to implement in either analog or digital domains with minimal changes to the bill of materials
  • JESD204B multi-device synchronization: Breaking down the requirements
    PDF, 146 Kb, 档案已发布: Apr 28, 2015
  • LMK04828 as a Clock Source for the ADS42JB69
    PDF, 1.4 Mb, 档案已发布: Nov 14, 2012
    ADS42JB69, ADS42LB69, LMK04828 LMK04828 as a clock source for the ADS42JB69
  • Analog Applications Journal 2Q 2015
    PDF, 2.5 Mb, 档案已发布: Apr 28, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, 修订版: A, 档案已发布: Jul 19, 2013
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, 修订版: A, 档案已发布: May 22, 2015
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015

模型线

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)