Datasheet Texas Instruments ADS54RF63 — 数据表
制造商 | Texas Instruments |
系列 | ADS54RF63 |
12位550MSPS射频采样模数转换器(ADC)
数据表
12-Bit 500-/550-MSPS Analog-to-Digital Converters datasheet
PDF, 2.0 Mb, 修订版: E, 档案已发布: Jul 1, 2009
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价格
状态
ADS54RF63IPFP | ADS54RF63IPFPR | |
---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | No | No |
打包
ADS54RF63IPFP | ADS54RF63IPFPR | |
---|---|---|
N | 1 | 2 |
Pin | 80 | 80 |
Package Type | PFP | PFP |
Industry STD Term | HTQFP | HTQFP |
JEDEC Code | S-PQFP-G | S-PQFP-G |
Package QTY | 96 | 1000 |
Carrier | JEDEC TRAY (10+1) | LARGE T&R |
Device Marking | ADS54RF63I | ADS54RF63I |
Width (mm) | 12 | 12 |
Length (mm) | 12 | 12 |
Thickness (mm) | 1 | 1 |
Pitch (mm) | .5 | .5 |
Max Height (mm) | 1.2 | 1.2 |
Mechanical Data | 下载 | 下载 |
参数化
Parameters / Models | ADS54RF63IPFP | ADS54RF63IPFPR |
---|---|---|
# Input Channels | 1 | 1 |
Analog Input BW, MHz | 2300 | 2300 |
Architecture | Pipeline | Pipeline |
DNL(Max), +/-LSB | 0.95 | 0.95 |
DNL(Typ), +/-LSB | 0.5 | 0.5 |
ENOB, Bits | 9.9 | 9.9 |
INL(Max), +/-LSB | 2.5 | 2.5 |
INL(Typ), +/-LSB | 0.7 | 0.7 |
Input Buffer | Yes | Yes |
Input Range, Vp-p | 2.2 | 2.2 |
Interface | Parallel LVDS | Parallel LVDS |
Operating Temperature Range, C | -40 to 85 | -40 to 85 |
Package Group | HTQFP | HTQFP |
Package Size: mm2:W x L, PKG | 80HTQFP: 196 mm2: 14 x 14(HTQFP) | 80HTQFP: 196 mm2: 14 x 14(HTQFP) |
Power Consumption(Typ), mW | 2250 | 2250 |
Rating | Catalog | Catalog |
Reference Mode | Ext,Int | Ext,Int |
Resolution, Bits | 12 | 12 |
SFDR, dB | 76 | 76 |
SINAD, dB | 61.3 | 61.3 |
SNR, dB | 62.6 | 62.6 |
Sample Rate(Max), MSPS | 550 | 550 |
生态计划
ADS54RF63IPFP | ADS54RF63IPFPR | |
---|---|---|
RoHS | Compliant | Compliant |
应用须知
- Clock jitter analyzed in the time domain, Part 1PDF, 302 Kb, 档案已发布: Aug 11, 2010
- Clock jitter analyzed in the time domain, Part 2PDF, 588 Kb, 档案已发布: Nov 15, 2010
- Clock jitter analyzed in the time domain, Part 3PDF, 627 Kb, 档案已发布: Sep 16, 2011
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- 3Q 2010 Issue Analog Applications JournalPDF, 1.5 Mb, 档案已发布: Aug 11, 2010
- High-Speed Analog-to-Digital Converter BasicsPDF, 1.1 Mb, 档案已发布: Jan 11, 2012
The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil - 3Q 2011 Issue Analog Applications JournalPDF, 1.4 Mb, 档案已发布: Sep 16, 2011
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TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, 档案已发布: Apr 28, 2009
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This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, 档案已发布: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
模型线
系列: ADS54RF63 (2)
制造商分类
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)