Datasheet Texas Instruments ADS5500-EP — 数据表

制造商Texas Instruments
系列ADS5500-EP
Datasheet Texas Instruments ADS5500-EP

14位125MSPS模数转换器(ADC)-增强型产品

数据表

ADS5500-EP datasheet
PDF, 939 Kb, 修订版: C, 档案已发布: Sep 2, 2008
从文件中提取

价格

状态

ADS5500MPAPEPADS5500MPAPREPV62/05613-01XEV62/05613-02XE
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNo

打包

ADS5500MPAPEPADS5500MPAPREPV62/05613-01XEV62/05613-02XE
N1234
Pin64646464
Package TypePAPPAPPAPPAP
Industry STD TermHTQFPHTQFPHTQFPHTQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY16010001000160
CarrierJEDEC TRAY (10+1)LARGE T&RLARGE T&RJEDEC TRAY (10+1)
Device MarkingADS5500MEPADS5500MEPADS5500MEPADS5500MEP
Width (mm)10101010
Length (mm)10101010
Thickness (mm)1111
Pitch (mm).5.5.5.5
Max Height (mm)1.21.21.21.2
Mechanical Data下载下载下载下载

参数化

Parameters / ModelsADS5500MPAPEP
ADS5500MPAPEP
ADS5500MPAPREP
ADS5500MPAPREP
V62/05613-01XE
V62/05613-01XE
V62/05613-02XE
V62/05613-02XE
# Input Channels1111
Analog Voltage AVDD(Max), V3.63.63.63.6
Analog Voltage AVDD(Min), V3333
ArchitecturePipelinePipelinePipelinePipeline
Digital Supply(Max), V3.63.63.63.6
Digital Supply(Min), V3333
ENOB, Bits11.311.311.311.3
INL(Max), +/-LSB8888
InterfaceParallel CMOSParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125
Package GroupHTQFPHTQFPHTQFPHTQFP
Package Size: mm2:W x L, PKG64HTQFP: 144 mm2: 12 x 12(HTQFP)64HTQFP: 144 mm2: 12 x 12(HTQFP)64HTQFP: 144 mm2: 12 x 12(HTQFP)64HTQFP: 144 mm2: 12 x 12(HTQFP)
Power Consumption(Typ), mW780780780780
RatingHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced Product
Reference ModeIntIntIntInt
Resolution, Bits14141414
SFDR, dB84848484
SNR, dB71717171
Sample Rate (max), SPS125MSPS125MSPS125MSPS125MSPS

生态计划

ADS5500MPAPEPADS5500MPAPREPV62/05613-01XEV62/05613-02XE
RoHSCompliantCompliantCompliantCompliant

应用须知

  • 14-Bit, 125-MSPS ADS5500 Evaluation
    PDF, 738 Kb, 档案已发布: Jan 18, 2005
  • Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev
    PDF, 627 Kb, 档案已发布: Jun 25, 2004
    Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC Drivers
    PDF, 273 Kb, 档案已发布: Apr 22, 2004
    Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • Clocking High-Speed Data Converters
    PDF, 310 Kb, 档案已发布: Jan 18, 2005
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015

模型线

制造商分类

  • Semiconductors> Space & High Reliability> Data Converter> Analog to Digital Converters