Datasheet Texas Instruments ADS7223 — 数据表

制造商	Texas Instruments
系列	ADS7223

12位1MSPS 4x2 / 2x2同步采样SAR ADC

数据表

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PDF, 1.4 Mb, 修订版: D, 档案已发布: Sep 2, 2017

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价格

状态

	ADS7223SRHBR	ADS7223SRHBT
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes	No

打包

	ADS7223SRHBR	ADS7223SRHBT
N	1	2
Pin	32	32
Package Type	RHB	RHB
Industry STD Term	VQFN	VQFN
JEDEC Code	S-PQFP-N	S-PQFP-N
Package QTY	3000	250
Carrier	LARGE T&R	SMALL T&R
Device Marking	7223	7223
Width (mm)	5	5
Length (mm)	5	5
Thickness (mm)	.9	.9
Pitch (mm)	.5	.5
Max Height (mm)	1	1
Mechanical Data	下载	下载

参数化

Parameters / Models	ADS7223SRHBR	ADS7223SRHBT
# Input Channels	4	4
Analog Voltage AVDD(Max), V	5.5	5.5
Analog Voltage AVDD(Min), V	2.7	2.7
Architecture	SAR	SAR
Digital Supply(Max), V	5.5	5.5
Digital Supply(Min), V	2.3	2.3
INL(Max), +/-LSB	0.5	0.5
Input Range(Max), V	5.5	5.5
Input Type	Differential,Pseudo-Differential	Differential,Pseudo-Differential
Integrated Features	N/A	N/A
Interface	SPI	SPI
Multi-Channel Configuration	Multiplexed,Simultaneous Sampling	Multiplexed,Simultaneous Sampling
Operating Temperature Range, C	-40 to 125	-40 to 125
Package Group	VQFN	VQFN
Package Size: mm2:W x L, PKG	32VQFN: 25 mm2: 5 x 5(VQFN)	32VQFN: 25 mm2: 5 x 5(VQFN)
Power Consumption(Typ), mW	47.2	47.2
Rating	Catalog	Catalog
Reference Mode	Ext,Int	Ext,Int
Resolution, Bits	12	12
SINAD, dB	72	72
SNR, dB	73	73
Sample Rate (max), SPS	1MSPS	1MSPS
Sample Rate(Max), MSPS	1	1
THD(Typ), dB	-86	-86

生态计划

	ADS7223SRHBR	ADS7223SRHBT
RoHS	Compliant	Compliant

应用须知

下载
Using the Sequencer and Pseudo-Differential Features of the ADS8363
PDF, 161 Kb, 档案已发布: May 21, 2014
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Interfacing to the ADS8363 Pseudo-Differential Operating Mode
PDF, 548 Kb, 档案已发布: Aug 4, 2014
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Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
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Determining Minimum Acquisition Times for SAR ADCs, part 2
PDF, 215 Kb, 档案已发布: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
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Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
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A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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Principles of Data Acquisition and Conversion (Rev. A)
PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015

模型线

系列: ADS7223 (2)

ADS7223SRHBR ADS7223SRHBT

制造商分类

Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)