Datasheet Texas Instruments ADS7823 — 数据表

制造商Texas Instruments
系列ADS7823
Datasheet Texas Instruments ADS7823

12位低功耗I2C串行采样模数转换器

数据表

ADS7823: 12-Bit, Sampling Analog-to-Digital Converter with I2C Interface datasheet
PDF, 630 Kb, 修订版: B, 档案已发布: Aug 27, 2003
从文件中提取

价格

状态

ADS7823E/250ADS7823E/250G4ADS7823E/2K5ADS7823EB/250ADS7823EB/250G4ADS7823EB/2K5
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesYesNoYesYesNo

打包

ADS7823E/250ADS7823E/250G4ADS7823E/2K5ADS7823EB/250ADS7823EB/250G4ADS7823EB/2K5
N123456
Pin888888
Package TypeDGKDGKDGKDGKDGKDGK
Industry STD TermVSSOPVSSOPVSSOPVSSOPVSSOPVSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY25025025002502502500
CarrierSMALL T&RSMALL T&RLARGE T&RSMALL T&RSMALL T&RLARGE T&R
Device MarkingB23B23B23B23B23B23
Width (mm)333333
Length (mm)333333
Thickness (mm).97.97.97.97.97.97
Pitch (mm).65.65.65.65.65.65
Max Height (mm)1.071.071.071.071.071.07
Mechanical Data下载下载下载下载下载下载

参数化

Parameters / ModelsADS7823E/250
ADS7823E/250
ADS7823E/250G4
ADS7823E/250G4
ADS7823E/2K5
ADS7823E/2K5
ADS7823EB/250
ADS7823EB/250
ADS7823EB/250G4
ADS7823EB/250G4
ADS7823EB/2K5
ADS7823EB/2K5
# Input Channels111111
Analog Voltage AVDD(Max), V5.255.255.255.255.255.25
Analog Voltage AVDD(Min), V4.754.754.754.754.754.75
ArchitectureSARSARSARSARSARSAR
Digital Supply(Max), V5.255.255.255.255.255.25
Digital Supply(Min), V4.754.754.754.754.754.75
INL(Max), +/-LSB111111
Input Range(Max), V5.255.255.255.255.255.25
Input TypeSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-Ended
Integrated FeaturesN/AN/AN/AN/AN/AN/A
InterfaceI2CI2CI2CI2CI2CI2C
Multi-Channel ConfigurationN/AN/AN/AN/AN/AN/A
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Package GroupVSSOPVSSOPVSSOPVSSOPVSSOPVSSOP
Package Size: mm2:W x L, PKG8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8VSSOP: 15 mm2: 4.9 x 3(VSSOP)
Power Consumption(Typ), mW1.21.21.21.21.21.2
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExtExtExtExtExtExt
Resolution, Bits121212121212
SINAD, dBN/AN/AN/AN/AN/AN/A
SNR, dB727272727272
Sample Rate (max), SPS50kSPS50kSPS50kSPS50kSPS50kSPS50kSPS
Sample Rate(Max), MSPS0.050.050.050.050.050.05
THD(Typ), dB-82-82-82-82-82-82

生态计划

ADS7823E/250ADS7823E/250G4ADS7823E/2K5ADS7823EB/250ADS7823EB/250G4ADS7823EB/2K5
RoHSCompliantCompliantCompliantCompliantCompliantCompliant

应用须知

  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, 档案已发布: Mar 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

模型线

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)