Datasheet Texas Instruments ADS801 — 数据表

制造商	Texas Instruments
系列	ADS801

数据表

价格

状态

打包

参数化

Parameters / Models	ADS801E	ADS801E/1K	ADS801U	ADS801UG4
# Input Channels	1	1	1	1
Analog Input BW, MHz			65
Analog Input BW(MHz)	65	65		65
Approx. Price (US$)	19.26 | 1ku	19.26 | 1ku		19.26 | 1ku
Architecture	Pipeline	Pipeline	Pipeline	Pipeline
DNL(Max), +/-LSB			0.4
DNL(Max)(+/-LSB)	0.4	0.4		0.4
DNL(Typ), +/-LSB			0.4
ENOB, Bits			10.3
ENOB(Bits)	10.3	10.3		10.3
INL(Max), +/-LSB			1.7
INL(Max)(+/-LSB)	1.7	1.7		1.7
INL(Typ), +/-LSB			1.7
Input Buffer	No	No	No
Input Range	2V (p-p)	2V (p-p)	2	2V (p-p)
Interface	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS
Operating Temperature Range, C			-40 to 85
Operating Temperature Range(C)	-40 to 85	-40 to 85		-40 to 85
Package Group	SOIC	SOIC	SOIC	SOIC
Package Size(mm2=WxL)				28SOIC: 184 mm2: 10.3 x 17.9
Package Size: mm2:W x L, PKG			28SOIC: 184 mm2: 10.3 x 17.9(SOIC)
Package Size: mm2:W x L (PKG)	28SOIC: 184 mm2: 10.3 x 17.9(SOIC)	28SOIC: 184 mm2: 10.3 x 17.9(SOIC)
Power Consumption(Typ), mW			270
Power Consumption(Typ)(mW)	270	270		270
Rating	Catalog	Catalog	Catalog	Catalog
Reference Mode	Ext Int	Ext Int	Ext,Int	Int Ext
Resolution, Bits			12
Resolution(Bits)	12	12		12
SFDR, dB			61
SFDR(dB)	61	61		61
SINAD, dB			66
SINAD(dB)	66	66		66
SNR, dB			64
SNR(dB)	64	64		64
Sample Rate (max)(SPS)				25MSPS
Sample Rate(Max), MSPS			25
Sample Rate(Max)(MSPS)	25	25

生态计划

应用须知

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• 下载
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  PDF, 805 Kb, 档案已发布: Sep 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527, which is capable of sampling up to 210 MSPS. To realize the full potential of thes
• 下载
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  PDF, 376 Kb, 档案已发布: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs
• 下载
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  PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies
• 下载
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  PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the refe
• 下载
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  PDF, 424 Kb, 档案已发布: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of
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  PDF, 64 Kb, 档案已发布: Oct 2, 2000
  It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration s
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  PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (ΔΣ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specificati
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制造商分类

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)