Datasheet Texas Instruments ADS8344 — 数据表

制造商Texas Instruments
系列ADS8344
Datasheet Texas Instruments ADS8344

16位,8通道串行输出采样模数转换器

数据表

16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital Converter datasheet
PDF, 1.1 Mb, 修订版: E, 档案已发布: Sep 28, 2006
从文件中提取

价格

状态

ADS8344EADS8344E/2K5ADS8344E/2K5G4ADS8344EBADS8344EB/2K5ADS8344EB/2K5G4ADS8344EBG4ADS8344EG4ADS8344NADS8344N/1KADS8344N/1KG4ADS8344NBADS8344NB/1KADS8344NB/1KG4ADS8344NBG4ADS8344NG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNoNoNoNoNoNoNoNoNo

打包

ADS8344EADS8344E/2K5ADS8344E/2K5G4ADS8344EBADS8344EB/2K5ADS8344EB/2K5G4ADS8344EBG4ADS8344EG4ADS8344NADS8344N/1KADS8344N/1KG4ADS8344NBADS8344NB/1KADS8344NB/1KG4ADS8344NBG4ADS8344NG4
N12345678910111213141516
Pin20202020202020202020202020202020
Package TypeDBQDBQDBQDBQDBQDBQDBQDBQDBDBDBDBDBDBDBDB
Industry STD TermSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY502500250050250025005050701000100070100010007070
CarrierTUBELARGE T&RLARGE T&RTUBELARGE T&RLARGE T&RTUBETUBETUBELARGE T&RLARGE T&RTUBELARGE T&RLARGE T&RTUBETUBE
Device MarkingADS8344EADS8344EADS8344EBADS8344EADS8344EADS8344EADS8344EBADS8344NBBBBBADS8344N
Width (mm)3.93.93.93.93.93.93.93.95.35.35.35.35.35.35.35.3
Length (mm)8.658.658.658.658.658.658.658.657.27.27.27.27.27.27.27.2
Thickness (mm)1.51.51.51.51.51.51.51.51.951.951.951.951.951.951.951.95
Pitch (mm).64.64.64.64.64.64.64.64.65.65.65.65.65.65.65.65
Max Height (mm)1.751.751.751.751.751.751.751.7522222222
Mechanical Data下载下载下载下载下载下载下载下载下载下载下载下载下载下载下载下载

参数化

Parameters / ModelsADS8344E
ADS8344E
ADS8344E/2K5
ADS8344E/2K5
ADS8344E/2K5G4
ADS8344E/2K5G4
ADS8344EB
ADS8344EB
ADS8344EB/2K5
ADS8344EB/2K5
ADS8344EB/2K5G4
ADS8344EB/2K5G4
ADS8344EBG4
ADS8344EBG4
ADS8344EG4
ADS8344EG4
ADS8344N
ADS8344N
ADS8344N/1K
ADS8344N/1K
ADS8344N/1KG4
ADS8344N/1KG4
ADS8344NB
ADS8344NB
ADS8344NB/1K
ADS8344NB/1K
ADS8344NB/1KG4
ADS8344NB/1KG4
ADS8344NBG4
ADS8344NBG4
ADS8344NG4
ADS8344NG4
# Input Channels8888888888888888
Analog Voltage AVDD(Max), V5.255.255.255.255.255.255.255.255.255.255.255.255.255.255.255.25
Analog Voltage AVDD(Min), V2.72.72.72.72.72.72.72.72.72.72.72.72.72.72.72.7
ArchitectureSARSARSARSARSARSARSARSARSARSARSARSARSARSARSARSAR
Digital Supply(Max), V5.255.255.255.255.255.255.255.255.255.255.255.255.255.255.255.25
Digital Supply(Min), V2.72.72.72.72.72.72.72.72.72.72.72.72.72.72.72.7
INL(Max), +/-LSB6666666666666666
Input Range(Max), V5.255.255.255.255.255.255.255.255.255.255.255.255.255.255.255.25
Input TypePseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-Ended
Integrated FeaturesN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/A
InterfaceSerialSerialSerialSerialSerialSerialSerialSerialSerialSerialSerialSerialSerialSerialSerialSerial
Multi-Channel ConfigurationMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexed
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Package GroupSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOP
Package Size: mm2:W x L, PKG20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)
Power Consumption(Typ), mW3.23.23.23.23.23.23.23.23.23.23.23.23.23.23.23.2
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExtExtExtExtExtExtExtExtExtExtExtExtExtExtExtExt
Resolution, Bits16161616161616161616161616161616
SINAD, dB86868686868686868686868686868686
SNR, dB89898989898989898989898989898989
Sample Rate (max), SPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS
Sample Rate(Max), MSPS0.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.1
THD(Typ), dB-90-90-90-90-90-90-90-90-90-90-90-90-90-90-90-90

生态计划

ADS8344EADS8344E/2K5ADS8344E/2K5G4ADS8344EBADS8344EB/2K5ADS8344EB/2K5G4ADS8344EBG4ADS8344EG4ADS8344NADS8344N/1KADS8344N/1KG4ADS8344NBADS8344NB/1KADS8344NB/1KG4ADS8344NBG4ADS8344NG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant

应用须知

  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, 档案已发布: Mar 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

模型线

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)