Datasheet Texas Instruments CD54AC74 — 数据表
制造商 | Texas Instruments |
系列 | CD54AC74 |
具有设置和复位功能的双路上升沿触发D型触发器
数据表
价格
状态
CD54AC74F3A | |
---|---|
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
打包
CD54AC74F3A | |
---|---|
N | 1 |
Pin | 14 |
Package Type | J |
Industry STD Term | CDIP |
JEDEC Code | R-GDIP-T |
Package QTY | 1 |
Carrier | TUBE |
Device Marking | CD54AC74F3A |
Width (mm) | 6.67 |
Length (mm) | 19.56 |
Thickness (mm) | 4.57 |
Pitch (mm) | 2.54 |
Max Height (mm) | 5.08 |
Mechanical Data | 下载 |
参数化
Parameters / Models | CD54AC74F3A |
---|---|
3-State Output | No |
Bits | 2 |
F @ Nom Voltage(Max), Mhz | 100 |
ICC @ Nom Voltage(Max), mA | 0.04 |
Input Type | CMOS |
Operating Temperature Range, C | -55 to 125 |
Output Drive (IOL/IOH)(Max), mA | 24/-24 |
Output Type | CMOS |
Package Group | CDIP |
Package Size: mm2:W x L, PKG | See datasheet (CDIP) |
Rating | Military |
Technology Family | AC |
VCC(Max), V | 5.5 |
VCC(Min), V | 1.5 |
tpd @ Nom Voltage(Max), ns | 114,12.7,9.1 |
生态计划
CD54AC74F3A | |
---|---|
RoHS | See ti.com |
应用须知
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, 修订版: A, 档案已发布: Feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, 档案已发布: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
模型线
系列: CD54AC74 (1)
制造商分类
- Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers