Datasheet Texas Instruments CD54ACT164F3A — 数据表
| 制造商 | Texas Instruments |
| 系列 | CD54ACT164 |
| 零件号 | CD54ACT164F3A |
8位串行输入/并行输出移位寄存器14-CDIP -55至125
数据表
8-Bit Serial-In/Parallel-Out Shift Register datasheet
PDF, 714 Kb, 修订版: A, 档案已发布: May 17, 2000
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 14 |
| Package Type | J |
| Industry STD Term | CDIP |
| JEDEC Code | R-GDIP-T |
| Package QTY | 1 |
| Carrier | TUBE |
| Device Marking | CD54ACT164F3A |
| Width (mm) | 6.67 |
| Length (mm) | 19.56 |
| Thickness (mm) | 4.57 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | 下载 |
参数化
| 3-State Output | No |
| Bits | 8 |
| F @ Nom Voltage(Max) | 90 Mhz |
| ICC @ Nom Voltage(Max) | 0.08 mA |
| Input Type | TTL |
| Operating Temperature Range | -55 to 125 C |
| Output Drive (IOL/IOH)(Max) | 24/-24 mA |
| Output Type | CMOS |
| Package Group | CDIP |
| Package Size: mm2:W x L | See datasheet (CDIP) PKG |
| Rating | Military |
| Technology Family | ACT |
| VCC(Max) | 5.5 V |
| VCC(Min) | 4.5 V |
| tpd @ Nom Voltage(Max) | 13.5 ns |
生态计划
| RoHS | See ti.com |
应用须知
- Selecting the Right Level Translation Solution (Rev. A)PDF, 313 Kb, 修订版: A, 档案已发布: Jun 22, 2004
Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati - CMOS Power Consumption and CPD Calculation (Rev. B)PDF, 89 Kb, 修订版: B, 档案已发布: Jun 1, 1997
Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale - Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, 修订版: A, 档案已发布: Feb 6, 2015
- Designing With Logic (Rev. C)PDF, 186 Kb, 修订版: C, 档案已发布: Jun 1, 1997
Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w - Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, 档案已发布: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
模型线
系列: CD54ACT164 (1)
- CD54ACT164F3A
制造商分类
- Semiconductors > Space & High Reliability > Logic Products > Flip-Flop/Latch/Registers