Datasheet Texas Instruments CD54HCT533 — 数据表
| 制造商 | Texas Instruments |
| 系列 | CD54HCT533 |
具有三态输出的高速CMOS逻辑八路反相透明锁存器
数据表
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 datasheet
PDF, 533 Kb, 修订版: C, 档案已发布: Jun 20, 2003
从文件中提取
价格
状态
| CD54HCT533F3A | |
|---|---|
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| CD54HCT533F3A | |
|---|---|
| N | 1 |
| Pin | 20 |
| Package Type | J |
| Industry STD Term | CDIP |
| JEDEC Code | R-GDIP-T |
| Package QTY | 1 |
| Carrier | TUBE |
| Device Marking | CD54HCT533F3A |
| Width (mm) | 6.92 |
| Length (mm) | 24.2 |
| Thickness (mm) | 4.57 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | 下载 |
参数化
| Parameters / Models | CD54HCT533F3A |
|---|---|
| 3-State Output | Yes |
| Bits | 8 |
| F @ Nom Voltage(Max), Mhz | 25 |
| ICC @ Nom Voltage(Max), mA | 0.08 |
| Input Type | TTL |
| Operating Temperature Range, C | -55 to 125 |
| Output Drive (IOL/IOH)(Max), mA | 6/-6 |
| Output Type | CMOS |
| Package Group | CDIP |
| Package Size: mm2:W x L, PKG | See datasheet (CDIP) |
| Rating | Military |
| Technology Family | HCT |
| VCC(Max), V | 5.5 |
| VCC(Min), V | 4.5 |
| tpd @ Nom Voltage(Max), ns | 43 |
生态计划
| CD54HCT533F3A | |
|---|---|
| RoHS | See ti.com |
应用须知
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, 修订版: A, 档案已发布: Feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, 档案已发布: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren - SN54/74HCT CMOS Logic Family Applications and RestrictionsPDF, 102 Kb, 档案已发布: May 1, 1996
The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal
模型线
系列: CD54HCT533 (1)
制造商分类
- Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers