Datasheet Texas Instruments CD74AC02 — 数据表

制造商Texas Instruments
系列CD74AC02
Datasheet Texas Instruments CD74AC02

四路2输入或非门

数据表

Qauadruple 2-Input Positive-NOR Gates datasheet
PDF, 982 Kb, 修订版: C, 档案已发布: Jun 12, 2002
从文件中提取

价格

状态

CD74AC02ECD74AC02EE4CD74AC02MCD74AC02M96CD74AC02M96G4CD74AC02ME4CD74AC02MG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNo

打包

CD74AC02ECD74AC02EE4CD74AC02MCD74AC02M96CD74AC02M96G4CD74AC02ME4CD74AC02MG4
N1234567
Pin14141414141414
Package TypeNNDDDDD
Industry STD TermPDIPPDIPSOICSOICSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY252550250025005050
CarrierTUBETUBETUBELARGE T&RLARGE T&RTUBETUBE
Device MarkingCD74AC02ECD74AC02EAC02MAC02MAC02MAC02MAC02M
Width (mm)6.356.353.913.913.913.913.91
Length (mm)19.319.38.658.658.658.658.65
Thickness (mm)3.93.91.581.581.581.581.58
Pitch (mm)2.542.541.271.271.271.271.27
Max Height (mm)5.085.081.751.751.751.751.75
Mechanical Data下载下载下载下载下载下载下载

参数化

Parameters / ModelsCD74AC02E
CD74AC02E
CD74AC02EE4
CD74AC02EE4
CD74AC02M
CD74AC02M
CD74AC02M96
CD74AC02M96
CD74AC02M96G4
CD74AC02M96G4
CD74AC02ME4
CD74AC02ME4
CD74AC02MG4
CD74AC02MG4
Bits4444444
F @ Nom Voltage(Max), Mhz100100100100100100100
ICC @ Nom Voltage(Max), mA0.080.080.080.080.080.080.08
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-2424/-2424/-24
Package GroupPDIPPDIPSOICSOICSOICSOICSOIC
Package Size: mm2:W x L, PKGSee datasheet (PDIP)See datasheet (PDIP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNo
Technology FamilyACACACACACACAC
VCC(Max), V5.55.55.55.55.55.55.5
VCC(Min), V1.51.51.51.51.51.51.5
Voltage(Nom), V1.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,5
tpd @ Nom Voltage(Max), ns131,14.6,10.4131,14.6,10.4131,14.6,10.4131,14.6,10.4131,14.6,10.4131,14.6,10.4131,14.6,10.4

生态计划

CD74AC02ECD74AC02EE4CD74AC02MCD74AC02M96CD74AC02M96G4CD74AC02ME4CD74AC02MG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYesYes

应用须知

  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, 档案已发布: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

模型线

制造商分类

  • Semiconductors> Logic> Gate> NOR Gate