Datasheet Texas Instruments CD74AC573 — 数据表

制造商Texas Instruments
系列CD74AC573
Datasheet Texas Instruments CD74AC573

具有三态输出的八路透明同相锁存器

数据表

Octal Transparent Latch, 3-State datasheet
PDF, 1.3 Mb, 档案已发布: Dec 3, 1998
从文件中提取

价格

状态

CD74AC573ECD74AC573MCD74AC573M96CD74AC573M96E4CD74AC573M96G4CD74AC573MG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNo

打包

CD74AC573ECD74AC573MCD74AC573M96CD74AC573M96E4CD74AC573M96G4CD74AC573MG4
N123456
Pin202020202020
Package TypeNDWDWDWDWDW
Industry STD TermPDIPSOICSOICSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY202520002000200025
CarrierTUBETUBELARGE T&RLARGE T&RLARGE T&RTUBE
Device MarkingCD74AC573EAC573MAC573MAC573MAC573MAC573M
Width (mm)6.357.57.57.57.57.5
Length (mm)24.3312.812.812.812.812.8
Thickness (mm)4.572.352.352.352.352.35
Pitch (mm)2.541.271.271.271.271.27
Max Height (mm)5.082.652.652.652.652.65
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参数化

Parameters / ModelsCD74AC573E
CD74AC573E
CD74AC573M
CD74AC573M
CD74AC573M96
CD74AC573M96
CD74AC573M96E4
CD74AC573M96E4
CD74AC573M96G4
CD74AC573M96G4
CD74AC573MG4
CD74AC573MG4
3-State OutputYesYesYesYesYesYes
Bits888888
F @ Nom Voltage(Max), Mhz100100100100100100
ICC @ Nom Voltage(Max), mA0.080.080.080.080.080.08
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-2424/-24
Package GroupPDIPSOICSOICSOICSOICSOIC
Package Size: mm2:W x L, PKGSee datasheet (PDIP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNo
Technology FamilyACACACACACAC
VCC(Max), V5.55.55.55.55.55.5
VCC(Min), V1.51.51.51.51.51.5
Voltage(Nom), V1.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,5
tpd @ Nom Voltage(Max), ns119,13.4,9.5119,13.4,9.5119,13.4,9.5119,13.4,9.5119,13.4,9.5119,13.4,9.5

生态计划

CD74AC573ECD74AC573MCD74AC573M96CD74AC573M96E4CD74AC573M96G4CD74AC573MG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYes

应用须知

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, 修订版: A, 档案已发布: Feb 6, 2015
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, 档案已发布: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

模型线

制造商分类

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch