[ /Title
(CD74
HC73,
CD74
HCT73
)
/Subject
(Dual
J-K
FlipFlop CD54HC73, CD74HC73,
CD74HCT73
Data sheet acquired from Harris Semiconductor
SCHS134E Dual J-K Flip-Flop with Reset
Negative-Edge Trigger February 1998 -Revised September 2003 Features Description Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times The ’HC73 and CD74HCT73 utilize silicon gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads. Asynchronous Reset Complementary Outputs These flip-flops have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input. This
device is functionally identical to the HC/HCT107 but differs …
