Datasheet Texas Instruments CDC111FN — 数据表

制造商Texas Instruments
系列CDC111
零件号CDC111FN
Datasheet Texas Instruments CDC111FN

3.3V LVPECL差分时钟驱动器28-PLCC

数据表

1-Line To 9-Line Differential LVPECL Clock Driver datasheet
PDF, 417 Kb, 修订版: G, 档案已发布: Aug 28, 1999
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

Pin28
Package TypeFN
Industry STD TermPLCC
JEDEC CodeS-PQCC-J
Package QTY37
CarrierTUBE
Device MarkingCDC111FN
Width (mm)11.51
Length (mm)11.51
Thickness (mm)4.06
Pitch (mm)1.27
Max Height (mm)4.57
Mechanical Data下载

参数化

Input Frequency(Max)500 MHz
Input LevelLVPECL
Number of Outputs9
Output Frequency(Max)500 MHz
Output LevelLVPECL
Package GroupPLCC
Package Size: mm2:W x L28PLCC: 132 mm2: 11.51 x 11.51(PLCC) PKG
RatingCatalog
VCC3.3 V
VCC Out3.3 V

生态计划

RoHSCompliant

应用须知

  • Using TI's CDC111/CDCVF111 W/ TLK3104SA Serial Transceiver for Gigabit Ethernet
    PDF, 79 Kb, 档案已发布: Oct 31, 2001
    This application report discusses jitter transfer of TI's CDC111/CDCVF111 clock drivers when driving TI's TLK3104 serial gigabit transceiver. This report summarizes worst case peak-to-peak and RMS jitter measurements taken at various points, as indicated in Figures 1 and 2. Two different clock sources are used to provide the reference clock signal for the clock drivers, and the output of each cloc
  • Jitter Performance of TI's CDC111/CDCVF111
    PDF, 149 Kb, 档案已发布: Oct 29, 2001
    This application report discusses various jitter measurements of TI?s CDC111/CDCVF111 while being driven by three different clock sources (VCXOs). The data contained in this report shows that the CDC111/CDCVF111 does not add more than 3 ps of peak-to-peak jitter. Hence, the CDC111 and CDCVF111 are ideal for various SONET and Gigabit Ethernet applications where skew and jitter are of major concern.
  • Output Jitter of CDC111/CDCVF111 in ASIC Networking Application
    PDF, 361 Kb, 档案已发布: Nov 2, 2001
    This report contains a number of peak-to-peak and cycle-to-cycle jitter measurements of TI?s CDC111 and CDCVF111 clock driver. In this ASIC event, both the CDC111/CDCVF111 clock drivers are used as a master clock distribution for the Gandalf Macro Family Testchip. Comprehensive jitter data as well as output signal levels were taken and thus are included for completeness.
  • DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
    PDF, 135 Kb, 档案已发布: Feb 19, 2003
  • AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
    PDF, 417 Kb, 修订版: C, 档案已发布: Oct 17, 2007
    This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

模型线

系列: CDC111 (1)
  • CDC111FN

制造商分类

  • Semiconductors > Clock and Timing > Clock Buffers > Differential