Datasheet Texas Instruments CDC2509 — 数据表

制造商Texas Instruments
系列CDC2509
Datasheet Texas Instruments CDC2509

具有三态输出的3.3V锁相环时钟驱动器

数据表

CDC2509: 3.3-V Phase-Lock Loop Clock Driver (Rev. C)
PDF, 614 Kb, 修订版: C, 档案已发布: Dec 2, 2004

价格

状态

CDC2509PWRCDC2509PWRG4
Lifecycle StatusNRND (Not recommended for new designs)NRND (Not recommended for new designs)
Manufacture's Sample AvailabilityNoNo

打包

CDC2509PWRCDC2509PWRG4
N12
Pin2424
Package TypePWPW
Industry STD TermTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY20002000
CarrierLARGE T&RLARGE T&R
Device MarkingCK2509CK2509
Width (mm)4.44.4
Length (mm)7.87.8
Thickness (mm)11
Pitch (mm).65.65
Max Height (mm)1.21.2
Mechanical Data下载下载

生态计划

CDC2509PWRCDC2509PWRG4
RoHSCompliantCompliant
Pb FreeYesYes

应用须知

  • Understanding the Differences Between CDC2509x/10x Devices
    PDF, 65 Kb, 档案已发布: Jan 8, 1999
    This application note provides information concerning the various revisions of the TI CDC2509/10 family of devices. In addition, it will assist designers with new and existing designs. Phase error information, both slope and absolute value, is provided to assist in the tuning process. Furthermore, a table summarizes important parameters for choosing the correct PLL. The table contains capacitance
  • High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)
    PDF, 109 Kb, 修订版: A, 档案已发布: Sep 23, 1998
    The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo

模型线

系列: CDC2509 (2)

制造商分类

  • Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers