Datasheet Texas Instruments CDC2509APWRG4 — 数据表
| 制造商 | Texas Instruments |
| 系列 | CDC2509A |
| 零件号 | CDC2509APWRG4 |
具有三态输出的3.3V锁相环时钟驱动器24-TSSOP 0至70
数据表
价格
状态
| Lifecycle Status | NRND (Not recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 24 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | CK2509A |
| Width (mm) | 4.4 |
| Length (mm) | 7.8 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
生态计划
| RoHS | Compliant |
| Pb Free | Yes |
应用须知
- Using CDC2509A/CDC2510A PLL With Spread Spectrum Clocking (SSC)PDF, 454 Kb, 档案已发布: Jan 5, 1999
This application note describes the CDC2509A/2510A [1] phase-lock loop clockdrivers and their use with spread spectrum clocking system. This application note gives SSC system performance measurements and parameter measurementinstructions. - High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)PDF, 109 Kb, 修订版: A, 档案已发布: Sep 23, 1998
The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo
模型线
系列: CDC2509A (2)
- CDC2509APWR CDC2509APWRG4
制造商分类
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers