Datasheet Texas Instruments CDC2516DGGR — 数据表
| 制造商 | Texas Instruments |
| 系列 | CDC2516 |
| 零件号 | CDC2516DGGR |
具有三态输出的3.3V锁相环时钟驱动器48-TSSOP
数据表
CDC2516: 3.3-V Phase-Lock Loop Clock Driver datasheet
PDF, 479 Kb, 修订版: C, 档案已发布: Dec 2, 2004
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
打包
| Pin | 48 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | CDC2516 |
| Width (mm) | 6.1 |
| Length (mm) | 12.5 |
| Thickness (mm) | 1.15 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 200 ps |
| Number of Outputs | 16 |
| Operating Frequency Range(Max) | 125 MHz |
| Operating Frequency Range(Min) | 25 MHz |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| t(phase error) | 400 ps |
| tsk(o) | 250 ps |
生态计划
| RoHS | Compliant |
应用须知
- High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)PDF, 109 Kb, 修订版: A, 档案已发布: Sep 23, 1998
The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo
模型线
系列: CDC2516 (2)
- CDC2516DGGR CDC2516DGGRG4
制造商分类
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers