Datasheet Texas Instruments CDC2516 — 数据表

制造商Texas Instruments
系列CDC2516
Datasheet Texas Instruments CDC2516

具有三态输出的3.3V锁相环时钟驱动器

数据表

CDC2516: 3.3-V Phase-Lock Loop Clock Driver datasheet
PDF, 479 Kb, 修订版: C, 档案已发布: Dec 2, 2004
从文件中提取

价格

状态

CDC2516DGGRCDC2516DGGRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesYes

打包

CDC2516DGGRCDC2516DGGRG4
N12
Pin4848
Package TypeDGGDGG
Industry STD TermTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY20002000
CarrierLARGE T&RLARGE T&R
Device MarkingCDC2516CDC2516
Width (mm)6.16.1
Length (mm)12.512.5
Thickness (mm)1.151.15
Pitch (mm).5.5
Max Height (mm)1.21.2
Mechanical Data下载下载

参数化

Parameters / ModelsCDC2516DGGR
CDC2516DGGR
CDC2516DGGRG4
CDC2516DGGRG4
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter), ps200200
Number of Outputs1616
Operating Frequency Range(Max), MHz125125
Operating Frequency Range(Min), MHz2525
Package GroupTSSOPTSSOP
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)
RatingCatalogCatalog
VCC, V3.33.3
t(phase error), ps400400
tsk(o), ps250250

生态计划

CDC2516DGGRCDC2516DGGRG4
RoHSCompliantCompliant

应用须知

  • High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)
    PDF, 109 Kb, 修订版: A, 档案已发布: Sep 23, 1998
    The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo

模型线

系列: CDC2516 (2)

制造商分类

  • Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers